文件名称:verilog
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verilog\rle
.......\...\tb
.......\...\..\bench.v
.......\...\..\bench_rle_rld.v
.......\...\..\rld_bench.v
.......\...\rtl
.......\...\...\jpeg_rld.v
.......\...\...\jpeg_rle.v
.......\...\...\jpeg_rle1.v
.......\...\...\jpeg_rzs.v
.......\interface
.......\.........\rtl
.......\.........\...\int.v
.......\idct
.......\....\tb
.......\....\..\tb_idct.v
.......\....\rtl
.......\....\...\dct.v
.......\....\...\dctu.v
.......\....\...\dctub.v
.......\....\...\dct_mac.v
.......\....\...\idct.v
.......\....\...\ptos.v
.......\....\...\table_indiv.v
.......\fifo
.......\....\fifofaq
.......\....\tb
.......\....\..\tb_fifotest.v
.......\....\..\tb_fifotest.v~
.......\....\..\tb_infifo.v
.......\....\..\tb_outfifo.v
.......\....\..\tb_outfifo.v~
.......\....\..\old revisions
.......\....\..\.............\tb_infifo_rev0.0.v
.......\....\..\.............\tb_infifo_rev0.1.v
.......\....\..\.............\tb_infifo_rev0.2.v
.......\....\..\.............\tb_infifo_rev0.3.v
.......\....\..\.............\tb_infifo_rev0.4.v
.......\....\..\.............\tb_infifo_rev0.5.v
.......\....\..\.............\tb_outfifo_rev0.0.v
.......\....\..\.............\tb_outfifo_rev0.5.v
.......\....\rtl
.......\....\...\bram_256x16.xco
.......\....\...\fifo.v
.......\....\...\fifo_test.v
.......\....\...\input_fifo.v
.......\....\...\output_fifo.v
.......\....\...\read_sm.v
.......\....\...\write_sm.v
.......\....\...\old revisions
.......\....\...\.............\fifo_rev0.0.v
.......\....\...\.............\fifo_rev1.0.v
.......\....\...\.............\fifo_rev_0.5.v
.......\....\...\.............\fifo_test_rev0.0.v
.......\....\...\.............\fifo_test_rev0.1.v
.......\....\...\.............\fifo_test_rev0.5.v
.......\....\...\.............\input_fifo_rev0.0.v
.......\....\...\.............\input_fifo_rev0.1.v
.......\....\...\.............\input_fifo_rev0.2.v
.......\....\...\.............\input_fifo_rev0.3.v
.......\....\...\.............\input_fifo_rev0.4.v
.......\....\...\.............\input_fifo_rev0.5.v
.......\....\...\.............\output_fifo_rev0.0.v
.......\....\...\.............\output_fifo_rev0.1.v
.......\....\...\.............\output_fifo_rev0.2.v
.......\....\...\.............\output_fifo_rev0.5.v
.......\....\...\.............\read_sm_rev0.0.v
.......\....\...\.............\read_sm_rev0.1.v
.......\....\...\.............\read_sm_rev0.2.v
.......\....\...\.............\read_sm_rev0.3.v
.......\....\...\.............\read_sm_rev0.5.v
.......\....\...\.............\write_sm_rev0.0.v
.......\....\...\.............\write_sm_rev0.1.v
.......\....\...\.............\write_sm_rev0.2.v
.......\....\...\.............\write_sm_rev0.3.v
.......\....\...\.............\write_sm_rev0.4.v
.......\....\...\.............\write_sm_rev0.5.v
.......\entropy
.......\.......\tb
.......\.......\..\bench_ref.v
.......\.......\..\bench_top.v
.......\.......\..\generic_dpram.v
.......\.......\..\generic_fifo_lfsr.v
.......\.......\..\lfsr.v
.......\.......\..\tb_dec.v
.......\.......\..\tb_henc.v
.......\.......\rtl
.......\.......\...\huffman_dec.v
.......\.......\...\huff_enc.v
.......\.......\...\huff_enc.v~
.......\encoder
.......\.......\tb
.......\.......\..\tb_enc.v
.......\.......\..\top_tb.v
.......\.......\..\top_tb.v~
.......\.......\..\top_tb1.v
.......\.......\..\old
.......\.......\..\...\tb_enc_rev0.v
.......\.......\..\...\tb_enc_rev1.v
.......\.......\..\...\top_tb_rev0.v