文件名称:Pll_prj
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介绍说明－－下载内容均来自于网络，请自行研究使用
FPGA中PLL模块的测试代码，代码通过例化一个PLL将25MHz系统时钟倍频到50MHz，然后通过两个不同频率时钟控制两个LED灯闪烁，通过闪烁频率可用观察PLL倍频效果-The FPGA PLL module test code, the code by instantiating a PLL to 25MHz system clock frequency doubling to 50MHz, and then by two different frequency clock control two LED lights flicker, flicker frequency can be used to observe the PLL multiplier effect
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Pll_prj\.sopc_builder\filters.xml
.......\db\logic_util_heursitic.dat
.......\..\pll.cbx.xml
.......\..\pll.cmp.rdb
.......\..\pll.cmp_merge.kpt
.......\..\pll.db_info
.......\..\pll.eda.qmsg
.......\..\pll.hier_info
.......\..\pll.hif
.......\..\pll.lpc.html
.......\..\pll.lpc.rdb
.......\..\pll.lpc.txt
.......\..\pll.map.bpm
.......\..\pll.map.cdb
.......\..\pll.map.hdb
.......\..\pll.map.kpt
.......\..\pll.map.logdb
.......\..\pll.map.qmsg
.......\..\pll.map_bb.cdb
.......\..\pll.map_bb.hdb
.......\..\pll.map_bb.logdb
.......\..\pll.pre_map.cdb
.......\..\pll.pre_map.hdb
.......\..\pll.rtlv.hdb
.......\..\pll.rtlv_sg.cdb
.......\..\pll.rtlv_sg_swap.cdb
.......\..\pll.sgdiff.cdb
.......\..\pll.sgdiff.hdb
.......\..\pll.sld_design_entry.sci
.......\..\pll.sld_design_entry_dsc.sci
.......\..\pll.smart_action.txt
.......\..\pll.syn_hier_info
.......\..\pll.tis_db_list.ddb
.......\..\prev_cmp_pll.qmsg
.......\greybox_tmp\cbx_args.txt
.......\incremental_db\compiled_partitions\pll.db_info
.......\..............\...................\pll.root_partition.hbdb.cdb
.......\..............\...................\pll.root_partition.map.cdb
.......\..............\...................\pll.root_partition.map.dpi
.......\..............\...................\pll.root_partition.map.hdb
.......\..............\...................\pll.root_partition.map.kpt
.......\..............\README
.......\pll.done
.......\pll.dpf
.......\pll.eda.rpt
.......\pll.flow.rpt
.......\pll.map.rpt
.......\pll.map.summary
.......\pll.qpf
.......\pll.qsf
.......\pll.v
.......\pll.v.bak
.......\pll_ctrl.ppf
.......\pll_ctrl.qip
.......\pll_ctrl.v
.......\pll_ctrl_bb.v
.......\pll_ctrl_inst.v
.......\pll_description.txt
.......\pll_nativelink_simulation.rpt
.......\simulation\modelsim\pll_prj.vt
.......\..........\........\pll_prj.vt.bak
.......\sopc_builder_log.txt
.......\incremental_db\compiled_partitions
.......\simulation\modelsim
.......\.sopc_builder
.......\db
.......\greybox_tmp
.......\incremental_db
.......\simulation
Pll_prj