文件名称:PLL_prj
- 所属分类：
- 单片机(51,AVR,MSP430等)
- 资源属性：
- 上传时间：
- 2012-11-26
- 文件大小：
- 32kb
- 下载次数：
- 0次
- 提 供 者：
- weiji*****
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
对锁相环频率综合器进行仿真计算，以优化环路参数。-PLL frequency synthesizer for the simulation to optimize the loop parameters.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
PLL_prj\de_sim.cfg
.......\de_sim.cfg.old
.......\hpeesofsim.cfg
.......\hpeesofsim.cfg.old
.......\layout.prf
.......\mil_layout.prf
.......\mil_schematic.prf
.......\momServer.log
.......\netlist.log
.......\...works\DPFDCP.ael
.......\........\DPFDCP.atf
.......\........\DPFDCP.dsn
.......\........\DVcoDivideByN.ael
.......\........\DVcoDivideByN.atf
.......\........\DVcoDivideByN.bak
.......\........\DVcoDivideByN.dsn
.......\........\PLL.ael
.......\........\PLL.atf
.......\........\PLL.bak
.......\........\PLL.dsn
.......\........\SigmaDelta4order.ael
.......\........\SigmaDelta4order.atf
.......\........\SigmaDelta4order.bak
.......\........\SigmaDelta4order.dsn
.......\........\untitled1.bak
.......\project.ads
.......\save_project_state.ael
.......\save_project_state.bak
.......\schematic.prf
.......\veriloga\DPFDCP.va
.......\........\DVcoDivideByN.va
.......\........\SigmaDelta4order.va
.......\data
.......\mom_dsn
.......\networks
.......\synthesis
.......\verification
.......\veriloga
PLL_prj
.......\de_sim.cfg.old
.......\hpeesofsim.cfg
.......\hpeesofsim.cfg.old
.......\layout.prf
.......\mil_layout.prf
.......\mil_schematic.prf
.......\momServer.log
.......\netlist.log
.......\...works\DPFDCP.ael
.......\........\DPFDCP.atf
.......\........\DPFDCP.dsn
.......\........\DVcoDivideByN.ael
.......\........\DVcoDivideByN.atf
.......\........\DVcoDivideByN.bak
.......\........\DVcoDivideByN.dsn
.......\........\PLL.ael
.......\........\PLL.atf
.......\........\PLL.bak
.......\........\PLL.dsn
.......\........\SigmaDelta4order.ael
.......\........\SigmaDelta4order.atf
.......\........\SigmaDelta4order.bak
.......\........\SigmaDelta4order.dsn
.......\........\untitled1.bak
.......\project.ads
.......\save_project_state.ael
.......\save_project_state.bak
.......\schematic.prf
.......\veriloga\DPFDCP.va
.......\........\DVcoDivideByN.va
.......\........\SigmaDelta4order.va
.......\data
.......\mom_dsn
.......\networks
.......\synthesis
.......\verification
.......\veriloga
PLL_prj