文件名称:fdivision

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2013-01-18
  • 文件大小:
  • 9.52mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • shao****
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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一个分频的quartus工程,用verilog写的,改变i的值可以实现任意分频,绝对原创-Quartus project a divide verilog write, change the value of i can achieve arbitrary divide absolute originality! ! !
(系统自动生成,下载前可以参看下载内容)

下载文件列表





fdivision

.........\db

.........\..\fdivision.atom_map.rvd

.........\..\fdivision.cbx.xml

.........\..\fdivision.cmp.rdb

.........\..\fdivision.cmp_merge.kpt

.........\..\fdivision.db_info

.........\..\fdivision.eda.qmsg

.........\..\fdivision.hier_info

.........\..\fdivision.hif

.........\..\fdivision.lpc.html

.........\..\fdivision.lpc.rdb

.........\..\fdivision.lpc.txt

.........\..\fdivision.map.bpm

.........\..\fdivision.map.cdb

.........\..\fdivision.map.hdb

.........\..\fdivision.map.kpt

.........\..\fdivision.map.logdb

.........\..\fdivision.map.qmsg

.........\..\fdivision.map_bb.cdb

.........\..\fdivision.map_bb.hdb

.........\..\fdivision.map_bb.logdb

.........\..\fdivision.pre_map.cdb

.........\..\fdivision.pre_map.hdb

.........\..\fdivision.rpp.qmsg

.........\..\fdivision.rtlv.hdb

.........\..\fdivision.rtlv_sg.cdb

.........\..\fdivision.rtlv_sg_swap.cdb

.........\..\fdivision.sgate.rvd

.........\..\fdivision.sgate_sm.rvd

.........\..\fdivision.sgdiff.cdb

.........\..\fdivision.sgdiff.hdb

.........\..\fdivision.sld_design_entry.sci

.........\..\fdivision.sld_design_entry_dsc.sci

.........\..\fdivision.smart_action.txt

.........\..\fdivision.syn_hier_info

.........\..\fdivision.tis_db_list.ddb

.........\..\fdivision.tmw_info

.........\..\logic_util_heursitic.dat

.........\..\prev_cmp_fdivision.qmsg

.........\fdivision.done

.........\fdivision.eda.rpt

.........\fdivision.flow.rpt

.........\fdivision.map.rpt

.........\fdivision.map.smsg

.........\fdivision.map.summary

.........\fdivision.qpf

.........\fdivision.qsf

.........\fdivision.v

.........\fdivision.v.bak

.........\fdivision_nativelink_simulation.rpt

.........\incremental_db

.........\..............\README

.........\..............\compiled_partitions

.........\..............\...................\fdivision.db_info

.........\..............\...................\fdivision.root_partition.map.cdb

.........\..............\...................\fdivision.root_partition.map.dpi

.........\..............\...................\fdivision.root_partition.map.hbdb.cdb

.........\..............\...................\fdivision.root_partition.map.hbdb.hb_info

.........\..............\...................\fdivision.root_partition.map.hbdb.hdb

.........\..............\...................\fdivision.root_partition.map.hbdb.sig

.........\..............\...................\fdivision.root_partition.map.hdb

.........\..............\...................\fdivision.root_partition.map.kpt

.........\simulation

.........\..........\modelsim

.........\..........\........\fdivision.vt

.........\..........\........\fdivision.vt.bak

.........\..........\........\fdivision_run_msim_rtl_verilog.do

.........\..........\........\fdivision_run_msim_rtl_verilog.do.bak

.........\..........\........\fdivision_run_msim_rtl_verilog.do.bak1

.........\..........\........\fdivision_run_msim_rtl_verilog.do.bak10

.........\..........\........\fdivision_run_msim_rtl_verilog.do.bak11

.........\..........\........\fdivision_run_msim_rtl_verilog.do.bak2

.........\..........\........\fdivision_run_msim_rtl_verilog.do.bak3

.........\..........\........\fdivision_run_msim_rtl_verilog.do.bak4

.........\..........\........\fdivision_run_msim_rtl_verilog.do.bak5

.........\..........\........\fdivision_run_msim_rtl_verilog.do.bak6

.........\..........\........\fdivision_run_msim_rtl_verilog.do.bak7

.........\..........\........\fdivision_run_msim_rtl_verilog.do.bak8

.........\..........\........\fdivision_run_msim_rtl_verilog.do.bak9

.........\..........\........\modelsim.ini

.........\..........\........\msim_transcript

.........\..........\........\rtl_work

.........\..........\........\........\_info

.........\..........\........\........\_temp

.........\..........\........\........\_vmake

.........\..........\........\........\fdivision

.........\..........\........\........\.........\_primary.dat

.........\..........\........\........\.........\_primary.dbs

.........\..........\........\........\.........\_primary.vhd

.........\..........\........\........\.........\verilog.prw

.........\..........\........\........\....

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