文件名称:VREILOG-HDL-clock-source-code
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VREILOG HDL clock source code，VREILOG HDL数字时钟 源代码。-VREILOG HDL clock source code
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下载文件列表
clock\clock.asm.rpt
.....\clock.bsf
.....\clock.done
.....\clock.fit.rpt
.....\clock.fit.smsg
.....\clock.fit.summary
.....\clock.flow.rpt
.....\clock.map.rpt
.....\clock.map.smsg
.....\clock.map.summary
.....\clock.pin
.....\clock.pof
.....\clock.qpf
.....\clock.qsf
.....\clock.sof
.....\clock.tan.rpt
.....\clock.tan.summary
.....\clock.v
.....\clock.v.bak
.....\clock1.bdf
.....\db\clock.db_info
.....\..\clock.eco.cdb
.....\..\clock.sld_design_entry.sci
.....\div_1k.bsf
.....\div_1k.v
.....\div_1k.v.bak
.....\div_4hz.bsf
.....\div_4hz.v
.....\div_4hz.v.bak
.....\scan_led.bsf
.....\scan_led.v
.....\scan_led.v.bak
.....\db
clock