文件名称:verilog-mac
介绍说明－－下载内容均来自于网络，请自行研究使用
这是一个以太网的mac程序，verilog写的，可方正 可实现-this is a mac implementation using verilog，you can emulate it or implement it directly
(系统自动生成,下载前可以参看下载内容)
下载文件列表
此代码是用Verilog实现的以太网接口\Chapter10 Sample\eth_clockgen.v
.................................\................\eth_cop.v
.................................\................\eth_crc.v
.................................\................\eth_defines.v
.................................\................\eth_fifo.v
.................................\................\eth_host.v
.................................\................\eth_maccontrol.v
.................................\................\eth_macstatus.v
.................................\................\eth_memory.v
.................................\................\eth_miim.v
.................................\................\eth_outputcontrol.v
.................................\................\eth_phy.v
.................................\................\eth_phy_defines.v
.................................\................\eth_random.v
.................................\................\eth_receivecontrol.v
.................................\................\eth_register.v
.................................\................\eth_registers.v
.................................\................\eth_rxaddrcheck.v
.................................\................\eth_rxcounters.v
.................................\................\eth_rxethmac.v
.................................\................\eth_rxstatem.v
.................................\................\eth_shiftreg.v
.................................\................\eth_spram_256x32.v
.................................\................\eth_top.v
.................................\................\eth_transmitcontrol.v
.................................\................\eth_txcounters.v
.................................\................\eth_txethmac.v
.................................\................\eth_txstatem.v
.................................\................\eth_wishbone.v
.................................\................\tb_cop.v
.................................\................\tb_ethernet.v
.................................\................\tb_ethernet_with_cop.v
.................................\................\tb_eth_defines.v
.................................\................\tb_eth_top.v
.................................\................\timescale.v
.................................\................\wb_bus_mon.v
.................................\................\wb_master32.v
.................................\................\wb_master_behavioral.v
.................................\................\wb_model_defines.v
.................................\................\wb_slave_behavioral.v
.................................\................\使用说明.txt
.................................\Chapter10 Sample
此代码是用Verilog实现的以太网接口
.................................\................\eth_cop.v
.................................\................\eth_crc.v
.................................\................\eth_defines.v
.................................\................\eth_fifo.v
.................................\................\eth_host.v
.................................\................\eth_maccontrol.v
.................................\................\eth_macstatus.v
.................................\................\eth_memory.v
.................................\................\eth_miim.v
.................................\................\eth_outputcontrol.v
.................................\................\eth_phy.v
.................................\................\eth_phy_defines.v
.................................\................\eth_random.v
.................................\................\eth_receivecontrol.v
.................................\................\eth_register.v
.................................\................\eth_registers.v
.................................\................\eth_rxaddrcheck.v
.................................\................\eth_rxcounters.v
.................................\................\eth_rxethmac.v
.................................\................\eth_rxstatem.v
.................................\................\eth_shiftreg.v
.................................\................\eth_spram_256x32.v
.................................\................\eth_top.v
.................................\................\eth_transmitcontrol.v
.................................\................\eth_txcounters.v
.................................\................\eth_txethmac.v
.................................\................\eth_txstatem.v
.................................\................\eth_wishbone.v
.................................\................\tb_cop.v
.................................\................\tb_ethernet.v
.................................\................\tb_ethernet_with_cop.v
.................................\................\tb_eth_defines.v
.................................\................\tb_eth_top.v
.................................\................\timescale.v
.................................\................\wb_bus_mon.v
.................................\................\wb_master32.v
.................................\................\wb_master_behavioral.v
.................................\................\wb_model_defines.v
.................................\................\wb_slave_behavioral.v
.................................\................\使用说明.txt
.................................\Chapter10 Sample
此代码是用Verilog实现的以太网接口