文件名称:4Verilog-FIFO
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FIFO的简单编程，该FIFO的深度为4，宽度为32，其接口类型见文件中的图标及其注释。-This example describes a synthesizable implementation of a FIFO. The FIFO depth and FIFO width in bits can be modified by simply changing the value of two parameters, `FWIDTH and `FDEPTH. For this example, the FIFO depth is 4 and the FIFO width is 32 bits. The input/output ports of the FIFO are shown in Figure F-1.
Figure F-1. FIFO Input/Output Ports
Figure F-1. FIFO Input/Output Ports
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4Verilog FIFO.txt