文件名称:Code-UART

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 4.22mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • cu***
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

code deverloper uart core
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Code UART\Fifo\db\logic_util_heursitic.dat

.........\....\..\prev_cmp_syn_fifo.qmsg

.........\....\..\syn_fifo.amm.cdb

.........\....\..\syn_fifo.asm.qmsg

.........\....\..\syn_fifo.asm.rdb

.........\....\..\syn_fifo.asm_labs.ddb

.........\....\..\syn_fifo.cbx.xml

.........\....\..\syn_fifo.cmp.bpm

.........\....\..\syn_fifo.cmp.cdb

.........\....\..\syn_fifo.cmp.hdb

.........\....\..\syn_fifo.cmp.kpt

.........\....\..\syn_fifo.cmp.logdb

.........\....\..\syn_fifo.cmp.rdb

.........\....\..\syn_fifo.cmp0.ddb

.........\....\..\syn_fifo.cmp1.ddb

.........\....\..\syn_fifo.cmp2.ddb

.........\....\..\syn_fifo.cmp_merge.kpt

.........\....\..\syn_fifo.db_info

.........\....\..\syn_fifo.eda.qmsg

.........\....\..\syn_fifo.fit.qmsg

.........\....\..\syn_fifo.hier_info

.........\....\..\syn_fifo.hif

.........\....\..\syn_fifo.idb.cdb

.........\....\..\syn_fifo.lpc.html

.........\....\..\syn_fifo.lpc.rdb

.........\....\..\syn_fifo.lpc.txt

.........\....\..\syn_fifo.map.bpm

.........\....\..\syn_fifo.map.cdb

.........\....\..\syn_fifo.map.hdb

.........\....\..\syn_fifo.map.kpt

.........\....\..\syn_fifo.map.logdb

.........\....\..\syn_fifo.map.qmsg

.........\....\..\syn_fifo.map_bb.cdb

.........\....\..\syn_fifo.map_bb.hdb

.........\....\..\syn_fifo.map_bb.logdb

.........\....\..\syn_fifo.pre_map.cdb

.........\....\..\syn_fifo.pre_map.hdb

.........\....\..\syn_fifo.rtlv.hdb

.........\....\..\syn_fifo.rtlv_sg.cdb

.........\....\..\syn_fifo.rtlv_sg_swap.cdb

.........\....\..\syn_fifo.sgdiff.cdb

.........\....\..\syn_fifo.sgdiff.hdb

.........\....\..\syn_fifo.sld_design_entry.sci

.........\....\..\syn_fifo.sld_design_entry_dsc.sci

.........\....\..\syn_fifo.smart_action.txt

.........\....\..\syn_fifo.sta.qmsg

.........\....\..\syn_fifo.sta.rdb

.........\....\..\syn_fifo.sta_cmp.7_slow.tdb

.........\....\..\syn_fifo.syn_hier_info

.........\....\..\syn_fifo.tis_db_list.ddb

.........\....\..\syn_fifo.tmw_info

.........\....\incremental_db\compiled_partitions\syn_fifo.db_info

.........\....\..............\...................\syn_fifo.root_partition.cmp.cdb

.........\....\..............\...................\syn_fifo.root_partition.cmp.dfp

.........\....\..............\...................\syn_fifo.root_partition.cmp.hdb

.........\....\..............\...................\syn_fifo.root_partition.cmp.kpt

.........\....\..............\...................\syn_fifo.root_partition.cmp.logdb

.........\....\..............\...................\syn_fifo.root_partition.cmp.rcfdb

.........\....\..............\...................\syn_fifo.root_partition.map.cdb

.........\....\..............\...................\syn_fifo.root_partition.map.dpi

.........\....\..............\...................\syn_fifo.root_partition.map.hbdb.cdb

.........\....\..............\...................\syn_fifo.root_partition.map.hbdb.hb_info

.........\....\..............\...................\syn_fifo.root_partition.map.hbdb.hdb

.........\....\..............\...................\syn_fifo.root_partition.map.hbdb.sig

.........\....\..............\...................\syn_fifo.root_partition.map.hdb

.........\....\..............\...................\syn_fifo.root_partition.map.kpt

.........\....\..............\README

.........\....\ram_dp_ar_aw.v

.........\....\ram_dp_ar_aw.v.bak

.........\....\simulation\modelsim\modelsim.ini

.........\....\..........\........\msim_transcript

.........\....\..........\........\rtl_work\syn_fifo\verilog.prw

.........\....\..........\........\........\........\verilog.psm

.........\....\..........\........\........\........\_primary.dat

.........\....\..........\........\........\........\_primary.dbs

.........\....\..........\........\........\........\_primary.vhd

.........\....\..........\........\........\........_tb\verilog.prw

.........\....\..........\........\........\...........\verilog.psm

.........\....\..........\........\........\...........\_primary.dat

.........\....\..........\........\........\...........\_primary.dbs

.........\....\..........\........\........\...........\_primary.vhd

.........\....\..........\........\........\_info

.......

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