文件名称:A-Fast-CRC-Implementation-on-FPGA
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CRC错误检测是一个非常
电信应用上常见的功能。
对提高数据速率的发展要求
更多和更sofisticated实现。
在本文中，我们提出了一个方法来实现
管道结构为基础的CRC功能
多项式除法。它非常有效地改善
高速性能，允许从1 Gb / s的数据传输速率
4千兆位/秒，基于FPGA implementions根据
并行化水平（8至32位）。- The CRC error detection is a very
common function on telecommunication applications. The evolution towards increasing data rates requires
more and more sofisticated
implementations. In this paper, we present a method to implement
the CRC function based on a pipeline structure for the
polynomial division. It improves very effectively the
speed performance, allowing data rates from 1 Gbits/s
to 4 Gbits/s on FPGA implementions, according to the
parallelisation level (8 to 32 bits).
电信应用上常见的功能。
对提高数据速率的发展要求
更多和更sofisticated实现。
在本文中，我们提出了一个方法来实现
管道结构为基础的CRC功能
多项式除法。它非常有效地改善
高速性能，允许从1 Gb / s的数据传输速率
4千兆位/秒，基于FPGA implementions根据
并行化水平（8至32位）。- The CRC error detection is a very
common function on telecommunication applications. The evolution towards increasing data rates requires
more and more sofisticated
implementations. In this paper, we present a method to implement
the CRC function based on a pipeline structure for the
polynomial division. It improves very effectively the
speed performance, allowing data rates from 1 Gbits/s
to 4 Gbits/s on FPGA implementions, according to the
parallelisation level (8 to 32 bits).
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A Fast CRC Implementation on FPGA Using a Pipelined Architecture for the polynomial division.pdf