文件名称:fifo
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actel 的同步硬件fifo的testbench,初学者可以看一下testbench怎么写的。-the testbench code of actel fpga,it is right for new learner~
(系统自动生成,下载前可以参看下载内容)
下载文件列表
fifo\designer\impl1\newCore.ide_des
....\........\.....\QWEQW.ide_des
....\........\.....\top.ide_des
....\fifo.prj
....\simulation\modelsim.ini
....\..........\modelsim.log
....\..........\presynth\new@core\verilog.prw
....\..........\........\........\verilog.psm
....\..........\........\........\_primary.dat
....\..........\........\........\_primary.dbs
....\..........\........\........\_primary.vhd
....\..........\........\testbench\verilog.prw
....\..........\........\.........\verilog.psm
....\..........\........\.........\_primary.dat
....\..........\........\.........\_primary.dbs
....\..........\........\.........\_primary.vhd
....\..........\........\_info
....\..........\........\_vmake
....\..........\run.do
....\..........\vsim.wlf
....\.martgen\newCore\newCore.cxf
....\........\.......\newCore.gen
....\........\.......\newCore.log
....\........\.......\newCore.v
....\........\newCore_work.ixf
....\........\smartgen.aws
....\.timulus\testbench.v
....\viewdraw\vf\project.lst
....\........\viewdraw.ini
....\designer\impl1\simulation
....\simulation\presynth\new@core
....\..........\........\testbench
....\..........\........\_temp
....\designer\impl1
....\simulation\presynth
....\.martgen\newCore
....\viewdraw\sch
....\........\sym
....\........\vf
....\........\wir
....\component
....\constraint
....\coreconsole
....\designer
....\hdl
....\phy_synthesis
....\simulation
....\smartgen
....\stimulus
....\synthesis
....\viewdraw
fifo
....\........\.....\QWEQW.ide_des
....\........\.....\top.ide_des
....\fifo.prj
....\simulation\modelsim.ini
....\..........\modelsim.log
....\..........\presynth\new@core\verilog.prw
....\..........\........\........\verilog.psm
....\..........\........\........\_primary.dat
....\..........\........\........\_primary.dbs
....\..........\........\........\_primary.vhd
....\..........\........\testbench\verilog.prw
....\..........\........\.........\verilog.psm
....\..........\........\.........\_primary.dat
....\..........\........\.........\_primary.dbs
....\..........\........\.........\_primary.vhd
....\..........\........\_info
....\..........\........\_vmake
....\..........\run.do
....\..........\vsim.wlf
....\.martgen\newCore\newCore.cxf
....\........\.......\newCore.gen
....\........\.......\newCore.log
....\........\.......\newCore.v
....\........\newCore_work.ixf
....\........\smartgen.aws
....\.timulus\testbench.v
....\viewdraw\vf\project.lst
....\........\viewdraw.ini
....\designer\impl1\simulation
....\simulation\presynth\new@core
....\..........\........\testbench
....\..........\........\_temp
....\designer\impl1
....\simulation\presynth
....\.martgen\newCore
....\viewdraw\sch
....\........\sym
....\........\vf
....\........\wir
....\component
....\constraint
....\coreconsole
....\designer
....\hdl
....\phy_synthesis
....\simulation
....\smartgen
....\stimulus
....\synthesis
....\viewdraw
fifo