文件名称:spi
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Verilog语言写的SPI接口（层次化设计，便于升级）-The implememt of SPI interface using Verilog HDL
(系统自动生成,下载前可以参看下载内容)
下载文件列表
spi\spi.v
...\spi_bitcounter.v
...\spi_bitcounter_rtl.v
...\spi_bytecounter.v
...\spi_bytecounter_rtl.v
...\spi_clkdiv_count.v
...\spi_clkdiv_count_rtl.v
...\spi_clock_gen.v
...\spi_comp3_ge.v
...\spi_comp3_ge_rtl.v
...\spi_comp3_se.v
...\spi_comp3_se_rtl.v
...\spi_control.v
...\spi_core.v
...\spi_cs_cnt.v
...\spi_cs_cnt_rtl.v
...\spi_equal3.v
...\spi_equal3_rtl.v
...\spi_fifo.v
...\spi_it.v
...\spi_map.v
...\spi_page_cnt.v
...\spi_page_cnt_rtl.v
...\spi_regs.v
...\spi_tx_rx.v
...\spi_waitcounter.v
...\spi_waitcounter_rtl.v
spi
...\spi_bitcounter.v
...\spi_bitcounter_rtl.v
...\spi_bytecounter.v
...\spi_bytecounter_rtl.v
...\spi_clkdiv_count.v
...\spi_clkdiv_count_rtl.v
...\spi_clock_gen.v
...\spi_comp3_ge.v
...\spi_comp3_ge_rtl.v
...\spi_comp3_se.v
...\spi_comp3_se_rtl.v
...\spi_control.v
...\spi_core.v
...\spi_cs_cnt.v
...\spi_cs_cnt_rtl.v
...\spi_equal3.v
...\spi_equal3_rtl.v
...\spi_fifo.v
...\spi_it.v
...\spi_map.v
...\spi_page_cnt.v
...\spi_page_cnt_rtl.v
...\spi_regs.v
...\spi_tx_rx.v
...\spi_waitcounter.v
...\spi_waitcounter_rtl.v
spi