文件名称:ADDER
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基于vhdl硬件描述语言设计的加法器电路 -Hardware descr iption language design based on vhdl adder circuit
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下载文件列表
1_ADDER\1_ADDER\1_ADDER.exp
.......\.......\files\L1.rpt
.......\.......\.....\L2.rpt
.......\.......\.....\L3.rpt
.......\.......\workdirs\aa\ADDER.sim
.......\.......\........\..\ADDER.syn
.......\.......\........\..\Anal.info
.......\.......\........\..\Anal.out
.......\.......\........\WORK\Anal.info
.......\.......\........\....\Anal.out
.......\.......\........\....\BIT_RTL_ADDER.sim
.......\.......\........\....\BIT_RTL_ADDER.syn
.......\1_adder.acf
.......\1_adder.hif
.......\1_adder.mmf
.......\1_ADDER.VHD
.......\bir_rtl_adder.acf
.......\bir_rtl_adder.hif
.......\bir_rtl_adder.mmf
.......\bir_rtl_adder.tdf
.......\bit_rtl_adder.acf
.......\bit_rtl_adder.hif
.......\bit_rtl_adder.mmf
.......\bit_rtl_adder.vhd
.......\LIB.DLS
.......\README.TXT
.......\U2268397.DLS
.......\1_ADDER\workdirs\aa
.......\.......\........\WORK
.......\.......\files
.......\.......\workdirs
.......\1_ADDER
1_ADDER
.......\.......\files\L1.rpt
.......\.......\.....\L2.rpt
.......\.......\.....\L3.rpt
.......\.......\workdirs\aa\ADDER.sim
.......\.......\........\..\ADDER.syn
.......\.......\........\..\Anal.info
.......\.......\........\..\Anal.out
.......\.......\........\WORK\Anal.info
.......\.......\........\....\Anal.out
.......\.......\........\....\BIT_RTL_ADDER.sim
.......\.......\........\....\BIT_RTL_ADDER.syn
.......\1_adder.acf
.......\1_adder.hif
.......\1_adder.mmf
.......\1_ADDER.VHD
.......\bir_rtl_adder.acf
.......\bir_rtl_adder.hif
.......\bir_rtl_adder.mmf
.......\bir_rtl_adder.tdf
.......\bit_rtl_adder.acf
.......\bit_rtl_adder.hif
.......\bit_rtl_adder.mmf
.......\bit_rtl_adder.vhd
.......\LIB.DLS
.......\README.TXT
.......\U2268397.DLS
.......\1_ADDER\workdirs\aa
.......\.......\........\WORK
.......\.......\files
.......\.......\workdirs
.......\1_ADDER
1_ADDER