文件名称:PCIbus_Verilog
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PCI总线（Slave）接口FPGA的实现代码，全部为Verilog语言源码文件，还包括测试代码，内附设计实用说明文档。-PCI Bus (Slave) interface to FPGA implementation of the code, all source code files for the Verilog language, but also test the code, included the design and practical documentation.
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下载文件列表
PCI_Altera\base_addr_chk.v
..........\config_mux.v
..........\glue.v
..........\pargen.v
..........\pci_top.v
..........\pci总线接口Verilog设计使用手册.pdf
..........\retry_count.v
..........\state_machine.v
..........\tstbench\bkend_daemon.v
..........\........\pci_clk_reset.v
..........\........\pci_stim.v
..........\........\pci_tb.v
..........\........\tasks.v
..........\waveperl.log
..........\tstbench
PCI_Altera
..........\config_mux.v
..........\glue.v
..........\pargen.v
..........\pci_top.v
..........\pci总线接口Verilog设计使用手册.pdf
..........\retry_count.v
..........\state_machine.v
..........\tstbench\bkend_daemon.v
..........\........\pci_clk_reset.v
..........\........\pci_stim.v
..........\........\pci_tb.v
..........\........\tasks.v
..........\waveperl.log
..........\tstbench
PCI_Altera