文件名称:MIPS-processor-Verilog-code
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原创，MIPS处理器Verilog源码，在FPGA实现单周期MIPS处理器，实现存储访问指令load word(lw)和store word(sw)，算术逻辑指令add、addi、sub、and、or和slt跳转指令branch equal(beq)和jump(j)-Original, achieves single-cycle MIPS processor MIPS processor Verilog source code, the FPGA, storage access instructions load word (lw) and store word (sw) arithmetic logic instructions add, addi, sub, and, or, and slt jump instructionbranch equal (beq, which) and jump (j)
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下载文件列表
MIPS处理器Verilog代码\Adder_PCShift.v
.....................\ALU.v
.....................\ALUOPUnit.v
.....................\CPU.v
.....................\CtrlUnit.v
.....................\DataMem.v
.....................\Expand.v
.....................\Inmemory.v
.....................\JpAD.v
.....................\MUX_32.v
.....................\MUX_5.v
.....................\PCAdder.v
.....................\PCCounter.v
.....................\Register.v
.....................\求最大公约数需要修改的模块\ALU.v
.....................\..........................\ALUOPUnit.v
.....................\..........................\Inmemory.v
.....................\..........................\Inmemory.v.bak
.....................\..........................\transcript
.....................\求最大公约数需要修改的模块
MIPS处理器Verilog代码
.....................\ALU.v
.....................\ALUOPUnit.v
.....................\CPU.v
.....................\CtrlUnit.v
.....................\DataMem.v
.....................\Expand.v
.....................\Inmemory.v
.....................\JpAD.v
.....................\MUX_32.v
.....................\MUX_5.v
.....................\PCAdder.v
.....................\PCCounter.v
.....................\Register.v
.....................\求最大公约数需要修改的模块\ALU.v
.....................\..........................\ALUOPUnit.v
.....................\..........................\Inmemory.v
.....................\..........................\Inmemory.v.bak
.....................\..........................\transcript
.....................\求最大公约数需要修改的模块
MIPS处理器Verilog代码