文件名称:DS-Verilog

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 3.27mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • syro*****
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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ad 采集 串行ADtlv2543和DATLV5618的接口程序

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(系统自动生成,下载前可以参看下载内容)

下载文件列表

DS-Verilog\DS\DS.prj

..........\..\说明.txt

..........\..\DS.prj.convert.7.3.bak

..........\..\component

..........\..\hdl\Adc.v

..........\..\...\SPI.v

..........\..\...\Distace.v

..........\..\hdl

..........\..\designer\impl1\Adc.tcl

..........\..\........\.....\Adc.ide_des

..........\..\........\.....\Distace.lok

..........\..\........\.....\Distace.adb

..........\..\........\.....\ada02724-1.tmp

..........\..\........\.....\Distace.adl

..........\..\........\.....\Adc.adb

..........\..\........\.....\designer.log

..........\..\........\.....\Adc.adl

..........\..\........\.....\Distace.tcl

..........\..\........\.....\Distace.ide_des

..........\..\........\.....\Distace-am.sdf

..........\..\........\.....\Distace.bit

..........\..\........\.....\Distace_ba.sdf

..........\..\........\.....\Distace_ba.v

..........\..\........\.....\Distace.vnm

..........\..\........\.....\flashpro.log

..........\..\........\.....\Distace.stp

..........\..\........\.....\......._fp\Distace.log

..........\..\........\.....\..........\Distace.pro

..........\..\........\.....\..........\projectData\Distace.stp

..........\..\........\.....\..........\projectData

..........\..\........\.....\Distace_fp

..........\..\........\.....\........dtf\master.gcf

..........\..\........\.....\...........\master-des.gcf

..........\..\........\.....\...........\import.log

..........\..\........\.....\...........\masks

..........\..\........\.....\...........\floorplan.gcf

..........\..\........\.....\...........\floorplan.gcf.old

..........\..\........\.....\...........\place.log

..........\..\........\.....\...........\last_placement.gcf

..........\..\........\.....\...........\mem_plmt.gcf

..........\..\........\.....\...........\masks.final

..........\..\........\.....\...........\route.log

..........\..\........\.....\...........\time.log

..........\..\........\.....\...........\bitgen.log

..........\..\........\.....\...........\initial_placement.gcf

..........\..\........\.....\...........\floorplan-des.gcf

..........\..\........\.....\Distace.dtf

..........\..\........\.....\Adc.dtf\master.gcf

..........\..\........\.....\.......\master-des.gcf

..........\..\........\.....\.......\import.log

..........\..\........\.....\.......\masks

..........\..\........\.....\.......\inverted_ports

..........\..\........\.....\.......\floorplan.gcf

..........\..\........\.....\Adc.dtf

..........\..\........\.....\simulation

..........\..\........\impl1

..........\..\designer

..........\..\stimulus

..........\..\phy_synthesis

..........\..\synthesis\Distace.srr

..........\..\.........\stdout.log

..........\..\.........\Distace.tlg

..........\..\.........\Distace.srs

..........\..\.........\Distace_syn.prj

..........\..\.........\Distace_syn.prd

..........\..\.........\Distace.srd

..........\..\.........\Distace.srm

..........\..\.........\Adc.srr

..........\..\.........\Adc.tlg

..........\..\.........\Distace.map

..........\..\.........\Distace.edn

..........\..\.........\Distace.sdf

..........\..\.........\Distace_sdc.sdc

..........\..\.........\Distace.areasrr

..........\..\.........\Adc_syn.prj

..........\..\.........\traplog.tlg

..........\..\.........\.recordref

..........\..\.........\Adc.srd

..........\..\.........\Adc.srm

..........\..\.........\Adc.map

..........\..\.........\Adc.edn

..........\..\.........\Adc.sdf

..........\..\.........\Adc_sdc.sdc

..........\..\.........\Adc.areasrr

..........\..\.........\Adc_syn.prd

..........\..\.........\Adc.srs

..........\..\.........\syntmp\Adc.plg

..........\..\.........\......\Adc.msg

..........\..\.........\......\Distace.msg

..........\..\.........\......\Distace.plg

..........\..\.........\syntmp

..........\..\synthesis

..........\..\.imulation\meminit.dat

..........\..\..........\modelsim.ini.sav

..........\..\..........\modelsim.ini

..........\..\simulation

..........\..\coreconsole

..........\..\smartgen\smartgen.aws

..........\..\smartgen

..........\..\viewdraw\viewdraw.ini

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