文件名称:fpga
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fpga功能实现有限字长响应FIR
用verilog编写-FPGA functionality in response to the realization of finite word-length FIR prepared using Verilog
用verilog编写-FPGA functionality in response to the realization of finite word-length FIR prepared using Verilog
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下载文件列表
fpga
....\add_12b.v
....\add_12b.v.bak
....\add_12b_tp.v
....\add_12b_tp.v.bak
....\add_16b.v
....\add_16b.v.bak
....\add_20b.v
....\add_20b.v.bak
....\add_20b_tp.v
....\add_20b_tp.v.bak
....\add_8b.v
....\add_8b.v.bak
....\add_8b_tp.v
....\add_8b_tp.v.bak
....\booth.v
....\booth.v.bak
....\booth_code.v
....\booth_code.v.bak
....\booth_code_tp.v
....\booth_code_tp.v.bak
....\booth_tp.v
....\booth_tp.v.bak
....\control.v
....\control.v.bak
....\control_tp.v
....\control_tp.v.bak
....\CSA4.v
....\CSA4.v.bak
....\CSA4_tp.v
....\CSA4_tp.v.bak
....\Dff.v
....\Dff.v.bak
....\Dff_tp.v
....\Dff_tp.v.bak
....\enter_x.v
....\enter_x.v.bak
....\enter_x_tp.v
....\enter_x_tp.v.bak
....\fir.cr.mti
....\fir.mpf
....\full_add1.v
....\full_add1.v.bak
....\full_add1_tp.v
....\full_add1_tp.v.bak
....\half_add1.v
....\half_add1.v.bak
....\half_add1_tp.v
....\half_add1_tp.v.bak
....\mux_h.v
....\mux_h.v.bak
....\mux_h_tp.v
....\mux_h_tp.v.bak
....\mux_x.v
....\mux_x.v.bak
....\mux_x_tp.v
....\mux_x_tp.v.bak
....\top.v
....\top.v.bak
....\top_tp.v
....\top_tp.v.bak
....\transcript
....\vish_stacktrace.vstf
....\vsim.wlf
....\wallace_tree_tp.v
....\wallace_tree_tp.v.bak
....\wallce_tree.v
....\wallce_tree.v.bak
....\wallce_tree_tp.v
....\wallce_tree_tp.v.bak
....\work
....\....\@c@s@a4
....\....\.......\verilog.asm
....\....\.......\_primary.dat
....\....\.......\_primary.vhd
....\....\@c@s@a4_tp
....\....\..........\verilog.asm
....\....\..........\_primary.dat
....\....\..........\_primary.vhd
....\....\@dff
....\....\....\verilog.asm
....\....\....\_primary.dat
....\....\....\_primary.vhd
....\....\@dff_tp
....\....\.......\verilog.asm
....\....\.......\_primary.dat
....\....\.......\_primary.vhd
....\....\add_12b
....\....\.......\verilog.asm
....\....\.......\_primary.dat
....\....\.......\_primary.vhd
....\....\add_12b_tp
....\....\..........\verilog.asm
....\....\..........\_primary.dat
....\....\..........\_primary.vhd
....\....\add_20b
....\....\.......\verilog.asm
....\....\.......\_primary.dat
....\....\.......\_primary.vhd
....\....\add_20b_tp
....\add_12b.v
....\add_12b.v.bak
....\add_12b_tp.v
....\add_12b_tp.v.bak
....\add_16b.v
....\add_16b.v.bak
....\add_20b.v
....\add_20b.v.bak
....\add_20b_tp.v
....\add_20b_tp.v.bak
....\add_8b.v
....\add_8b.v.bak
....\add_8b_tp.v
....\add_8b_tp.v.bak
....\booth.v
....\booth.v.bak
....\booth_code.v
....\booth_code.v.bak
....\booth_code_tp.v
....\booth_code_tp.v.bak
....\booth_tp.v
....\booth_tp.v.bak
....\control.v
....\control.v.bak
....\control_tp.v
....\control_tp.v.bak
....\CSA4.v
....\CSA4.v.bak
....\CSA4_tp.v
....\CSA4_tp.v.bak
....\Dff.v
....\Dff.v.bak
....\Dff_tp.v
....\Dff_tp.v.bak
....\enter_x.v
....\enter_x.v.bak
....\enter_x_tp.v
....\enter_x_tp.v.bak
....\fir.cr.mti
....\fir.mpf
....\full_add1.v
....\full_add1.v.bak
....\full_add1_tp.v
....\full_add1_tp.v.bak
....\half_add1.v
....\half_add1.v.bak
....\half_add1_tp.v
....\half_add1_tp.v.bak
....\mux_h.v
....\mux_h.v.bak
....\mux_h_tp.v
....\mux_h_tp.v.bak
....\mux_x.v
....\mux_x.v.bak
....\mux_x_tp.v
....\mux_x_tp.v.bak
....\top.v
....\top.v.bak
....\top_tp.v
....\top_tp.v.bak
....\transcript
....\vish_stacktrace.vstf
....\vsim.wlf
....\wallace_tree_tp.v
....\wallace_tree_tp.v.bak
....\wallce_tree.v
....\wallce_tree.v.bak
....\wallce_tree_tp.v
....\wallce_tree_tp.v.bak
....\work
....\....\@c@s@a4
....\....\.......\verilog.asm
....\....\.......\_primary.dat
....\....\.......\_primary.vhd
....\....\@c@s@a4_tp
....\....\..........\verilog.asm
....\....\..........\_primary.dat
....\....\..........\_primary.vhd
....\....\@dff
....\....\....\verilog.asm
....\....\....\_primary.dat
....\....\....\_primary.vhd
....\....\@dff_tp
....\....\.......\verilog.asm
....\....\.......\_primary.dat
....\....\.......\_primary.vhd
....\....\add_12b
....\....\.......\verilog.asm
....\....\.......\_primary.dat
....\....\.......\_primary.vhd
....\....\add_12b_tp
....\....\..........\verilog.asm
....\....\..........\_primary.dat
....\....\..........\_primary.vhd
....\....\add_20b
....\....\.......\verilog.asm
....\....\.......\_primary.dat
....\....\.......\_primary.vhd
....\....\add_20b_tp