文件名称:AHB_to_Wishbone_Verilog
介绍说明－－下载内容均来自于网络，请自行研究使用
该源代码包是AHB总线到Wishbone总线的交接器，包括以下4个部分：RTL源代码，测试平台，软件测试程序，说明文档。-This source package is the AHB bus to Wishbone bus bridge(wrapper).It has the following 4 parts: RTL codes, testbench, software simulating files, help documents.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
AHB_to_Wishbone_Verilog\bench\ahb2wb_tb.v
.......................\doc\ahb_doc.doc
.......................\...\ahb_doc.pdf
.......................\...\ahb_doc.sxw
.......................\sim\modelsim.ini
.......................\...\run.mti
.......................\.rc\ahb2wb.v
.......................\bench
.......................\doc
.......................\sim
.......................\src
AHB_to_Wishbone_Verilog
.......................\doc\ahb_doc.doc
.......................\...\ahb_doc.pdf
.......................\...\ahb_doc.sxw
.......................\sim\modelsim.ini
.......................\...\run.mti
.......................\.rc\ahb2wb.v
.......................\bench
.......................\doc
.......................\sim
.......................\src
AHB_to_Wishbone_Verilog