搜索资源列表
leon3-altera-ep2s60-sdr
- ahb sdram interface.arm cpu series,include controller
ahb_system_generator.tar
- An AHB system is made of masters slaves and interconnections. A general approach to include all possible "muxed" implementation of multi layered AHB systems and arbitrated AHB ones can be thought as an acyclic graph wher
CorePCIF_AHB_hb
- AHB to PCI Structure for FPGA/Asic Designer
SLAVERAM
- AHB slave 的一个简单的原型程序，通过参考该程序，可以写出相应的ahb slave 代码-AHB slave prototype of a simple procedure, by referring to the program, you can write the corresponding code ahb slave
appnote65_quickmips_ahb_interface_design_example.r
- appnote65_quickmips_ahb_interface_design_example AHB接口设计-appnote65_quickmips_ahb_interface_design_exampleAHB Interface Design
ahb2ahb
- AMBA总线AHB TO AHB bridge-AMBA bus AHB TO AHB bridge
DW_8b10b_enc.v.tar
- amba ahb protocol with test benches
ahb_interface
- AHB BUS, Master Slave Arbiter -- example-AHB BUS, Master Slave Arbiter
ahb2wishbone_latest.tar
- opencore ahb to wishbone bus verilog code
amba
- doc file on AMBA...advanced microcontroller bus architecture ...basic og amba ahb, asb, apb
camera_up
- Camera Interface模块是视频输入转换存储模块。该模块一端接通用的video camera设备，另一端接AHB总线。实现了将Camera捕捉到的数据进行转换、并通过DMA存储到memory中。该IP支持ITU-R BT 601/656 8-bit 模式。支持YCbCr, RGB格式输入。可以将camera产生的YCbCr信号转换成24bit RGB 信号，然后下采样生成16bit RGB 5：6：5的LCD能直接读取显示的数
ahb_master1
- this is a code of AMBA AHB master protocol in verilog
tb_ahb_master
- this is a AMBA AHB code for master.
AHB
- 用VHDL编写的AMBA总线的AHB代码-Written with the VHDL code for AMBA bus AHB
AMBA-AHB-APB-BUS
- 常见ARM架构的AMBA、AHB、APB总线的介绍，对ARM的总线有个清晰的了解，对各模块的关系也可深入了解-Common ARM architecture AMBA, AHB, APB bus introduction of ARM' s have a clear understanding of the bus, on the relationship between the modules can also be in-de
AHB
- 基于混合优先权算法的AHB总线仲裁器的设计-Hybrid algorithm based on priority AHB bus arbiter design
AHB-BUS-AND-SLAVE-CODE-USING-VERILOG
- AHB总线下的slave代码verilog-AHB BUS AND SLAVE CODE USING VERILOG
ahb
- verilog实现AHB总线上的主从控制，在fpga上验证通过(Verilog realizes master slave control on AHB bus and verifies it on FPGA)
AHB RAM
- Verilog写的 AHB总线接口的SRAM代码，带Testbench。(Verilog wrote AHB bus interface SRAM code with Testbench.)
AHB-task-slave-master
- ahb master行为级模型，ahb slave模型(AHB master behavior level model, AHB slave model)