文件名称:FPU

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [Windows] [程序]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 680kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • Ru***
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

Verilog HDL code for implementation of double floating point architecture. Program takes care of diffent exceptions like overflow, underflow, NaN etc
(系统自动生成,下载前可以参看下载内容)

下载文件列表

FPU\FPU_2nd\FPU_2nd\build_simx.bat

...\.......\.......\debsmall.txt

...\.......\.......\dump.bk

...\.......\.......\dump.btim

...\.......\.......\errors.log

...\.......\.......\files_to_build.txt

...\.......\.......\fpu.v

...\.......\.......\fpu.v~

...\.......\.......\FPU_2nd.bld

...\.......\.......\FPU_2nd.dsk

...\.......\.......\FPU_2nd.hpj

...\.......\.......\fpu_add.v

...\.......\.......\fpu_add.v~

...\.......\.......\fpu_div.v

...\.......\.......\fpu_div.v~

...\.......\.......\fpu_double.v

...\.......\.......\fpu_double.v~

...\.......\.......\fpu_exceptions.v

...\.......\.......\fpu_exceptions.v~

...\.......\.......\fpu_mul.v

...\.......\.......\fpu_mul.v~

...\.......\.......\fpu_round.v

...\.......\.......\fpu_round.v~

...\.......\.......\fpu_sub.v

...\.......\.......\fpu_sub.v~

...\.......\.......\fpu_TB.v

...\.......\.......\fpu_TB.v~

...\.......\.......\lib\verilog\cds.lib

...\.......\.......\...\.......\hdl.var

...\.......\.......\...\.......\inputfiles.txt

...\.......\.......\...\.......\sram.v

...\.......\.......\...\.......\tbfifosemaphore.v

...\.......\.......\...\.......\tbsyslog.v

...\.......\.......\...\.......\tb_clock_max.v

...\.......\.......\...\.......\tb_clock_max_inverted.v

...\.......\.......\...\.......\tb_clock_min.v

...\.......\.......\...\.......\tb_clock_minmax.v

...\.......\.......\...\.......\tb_clock_minmax_inverted.v

...\.......\.......\...\.......\tb_clock_min_inverted.v

...\.......\.......\...\.......\tb_clock_typ.v

...\.......\.......\...\.......\tb_clock_typ_inverted.v

...\.......\.......\...\.......\tb_divider_clock.v

...\.......\.......\...\.......\tb_divider_clock_minmax.v

...\.......\.......\run_simx.bat

...\.......\.......\simulation.log

...\.......\.......\simulation.log~

...\.......\.......\simwrap-sim.log

...\.......\.......\simx.log

...\.......\.......\simxsim.log

...\.......\.......\.......32\.obj-release\.sconsign.dblite

...\.......\.......\.........\............\syncad_sim_code.obj

...\.......\.......\.........\............\syncad_sim_constant.obj

...\.......\.......\.........\............\syncad_sim_data.obj

...\.......\.......\.........\............\syncad_sim_debugsymbols.obj

...\.......\.......\.........\............\syncad_sim_init.obj

...\.......\.......\.........\............\syncad_sim_main.obj

...\.......\.......\.........\............\syncad_sim_process.obj

...\.......\.......\.........\............\syncad_sim_source_info.obj

...\.......\.......\.........\............\syncad_sim_types.obj

...\.......\.......\.........\database.binarch

...\.......\.......\.........\simdatabase.bin

...\.......\.......\.........\simxsim.dll

...\.......\.......\.........\simxsim.exp

...\.......\.......\.........\simxsim.lib

...\.......\.......\StimulusAndResults.bk

...\.......\.......\StimulusAndResults.btim

...\.......\.......\StimulusAndResultsTim.v

...\.......\.......\syncad.v

...\.......\.......\wavelib.v

...\.......\.......\wavelib_exact.v

...\.......\.......\wavelib_inertial.v

...\.......\.......\wavelib_standard.v

...\.......\.......\wavelib_transport.v

...\.......\.......\waveperl.log

...\FPU.docx

...\Program Specifications.docx

...\FPU_2nd\FPU_2nd\lib\verilog

...\.......\.......\simxsim32\.obj-release

...\.......\.......\.........\.obj-debug

...\.......\.......\lib

...\.......\.......\simxsim32

...\.......\FPU_2nd

...\FPU_2nd

FPU

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