文件名称:ddr
介绍说明－－下载内容均来自于网络，请自行研究使用
基于FPGA的ddr控制器的设计与实现，verilog，ISE-FPGA-based controller design and implementation of ddr, verilog, ISE
(系统自动生成,下载前可以参看下载内容)
下载文件列表
ddr\altclklock.v
...\ddr.cr.mti
...\ddr.mpf
...\ddr_Command.v
...\ddr_control_interface.v
...\ddr_data_path.v
...\ddr_sdram.v
...\ddr_sdram_tb.v
...\note.txt
...\Params.v
...\pll1.v
...\transcript
...\work\_info
...\....\pll1\transcript
...\....\....\verilog.asm
...\....\....\_primary.dat
...\....\....\_primary.vhd
...\....\mt46v4m16\verilog.asm
...\....\.........\_primary.dat
...\....\.........\_primary.vhd
...\....\ddr_sdram_tb\verilog.asm
...\....\............\_primary.dat
...\....\............\_primary.vhd
...\....\.........\verilog.asm
...\....\.........\_primary.dat
...\....\.........\_primary.vhd
...\....\....data_path\verilog.asm
...\....\.............\_primary.dat
...\....\.............\_primary.vhd
...\....\....control_interface\verilog.asm
...\....\.....................\_primary.dat
...\....\.....................\_primary.vhd
...\....\......mmand\verilog.asm
...\....\...........\_primary.dat
...\....\...........\_primary.vhd
...\....\altclklock\verilog.asm
...\....\..........\_primary.dat
...\....\..........\_primary.vhd
...\chart\图9-16.bmp
...\.....\图9-17.bmp
...\.....\图9-19.bmp
...\.....\图9-20.bmp
...\.....\图9-22.bmp
...\.....\图9-23.bmp
...\.....\图9-26.bmp
...\.....\图9-27.bmp
...\work\pll1
...\....\mt46v4m16
...\....\ddr_sdram_tb
...\....\ddr_sdram
...\....\ddr_data_path
...\....\ddr_control_interface
...\....\ddr_command
...\....\altclklock
...\work
...\chart
ddr
...\ddr.cr.mti
...\ddr.mpf
...\ddr_Command.v
...\ddr_control_interface.v
...\ddr_data_path.v
...\ddr_sdram.v
...\ddr_sdram_tb.v
...\note.txt
...\Params.v
...\pll1.v
...\transcript
...\work\_info
...\....\pll1\transcript
...\....\....\verilog.asm
...\....\....\_primary.dat
...\....\....\_primary.vhd
...\....\mt46v4m16\verilog.asm
...\....\.........\_primary.dat
...\....\.........\_primary.vhd
...\....\ddr_sdram_tb\verilog.asm
...\....\............\_primary.dat
...\....\............\_primary.vhd
...\....\.........\verilog.asm
...\....\.........\_primary.dat
...\....\.........\_primary.vhd
...\....\....data_path\verilog.asm
...\....\.............\_primary.dat
...\....\.............\_primary.vhd
...\....\....control_interface\verilog.asm
...\....\.....................\_primary.dat
...\....\.....................\_primary.vhd
...\....\......mmand\verilog.asm
...\....\...........\_primary.dat
...\....\...........\_primary.vhd
...\....\altclklock\verilog.asm
...\....\..........\_primary.dat
...\....\..........\_primary.vhd
...\chart\图9-16.bmp
...\.....\图9-17.bmp
...\.....\图9-19.bmp
...\.....\图9-20.bmp
...\.....\图9-22.bmp
...\.....\图9-23.bmp
...\.....\图9-26.bmp
...\.....\图9-27.bmp
...\work\pll1
...\....\mt46v4m16
...\....\ddr_sdram_tb
...\....\ddr_sdram
...\....\ddr_data_path
...\....\ddr_control_interface
...\....\ddr_command
...\....\altclklock
...\work
...\chart
ddr