文件名称:verilog-usb--protel-design
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基于FPGA的usb2.0 ip核设计，所用的语言是verilog-FPGA-based usb2.0 ip core design, the language used is the verilog
(系统自动生成,下载前可以参看下载内容)
下载文件列表
verilog usb protel design\usbf_crc16.v
..........................\usbf_crc5.v
..........................\usbf_defines.v
..........................\usbf_ep_rf.v
..........................\usbf_ep_rf_dummy.v
..........................\usbf_idma.v
..........................\usbf_mem_arb.v
..........................\usbf_pa.v
..........................\usbf_pd.v
..........................\usbf_pe.v
..........................\usbf_pl.v
..........................\usbf_rf.v
..........................\usbf_top.v
..........................\usbf_utmi_if.v
..........................\usbf_utmi_ls.v
..........................\usbf_wb.v
verilog usb protel design
..........................\usbf_crc5.v
..........................\usbf_defines.v
..........................\usbf_ep_rf.v
..........................\usbf_ep_rf_dummy.v
..........................\usbf_idma.v
..........................\usbf_mem_arb.v
..........................\usbf_pa.v
..........................\usbf_pd.v
..........................\usbf_pe.v
..........................\usbf_pl.v
..........................\usbf_rf.v
..........................\usbf_top.v
..........................\usbf_utmi_if.v
..........................\usbf_utmi_ls.v
..........................\usbf_wb.v
verilog usb protel design