文件名称:dct
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离散余弦变换的设计源代码以及测试源代码和仿真图-Design of discrete cosine transform source code and test source code and simulation plan
(系统自动生成,下载前可以参看下载内容)
下载文件列表
10.3\dct.cr.mti
....\dct.mpf
....\dct.v
....\dct_cos_table.v
....\dct_mac.v
....\dct_syn.v
....\dct_testbench.v
....\dctu.v
....\dctub.v
....\fdct.v
....\qnr.cr.mti
....\timescale.v
....\transcript
....\vsim.wlf
....\zigzag.v
....\work\_info
....\....\zigzag\_primary.dat
....\....\......\_primary.vhd
....\....\......\verilog.asm
....\....\fdct\_primary.dat
....\....\....\_primary.vhd
....\....\....\verilog.asm
....\....\dctub\_primary.dat
....\....\.....\_primary.vhd
....\....\.....\verilog.asm
....\....\....\_primary.dat
....\....\....\_primary.vhd
....\....\....\verilog.asm
....\....\..._testbench\_primary.dat
....\....\.............\_primary.vhd
....\....\.............\verilog.asm
....\....\....syn\_primary.dat
....\....\.......\_primary.vhd
....\....\.......\verilog.asm
....\....\....mac\_primary.dat
....\....\.......\_primary.vhd
....\....\.......\verilog.asm
....\....\...\_primary.dat
....\....\...\_primary.vhd
....\....\...\verilog.asm
....\....\bench_top\_primary.dat
....\....\.........\_primary.vhd
....\....\.........\verilog.asm
....\.ave\Thumbs.db
....\....\dct.bmp
....\....\dct_testbench.bmp
....\....\dctu.bmp
....\....\dctub.bmp
....\....\fdct.bmp
....\....\zigzag.bmp
....\chart\Thumbs.db
....\.....\图10-18.bmp
....\.....\图10-19.bmp
....\.....\图10-20.bmp
....\.....\图10-22.bmp
....\.....\图10-23.bmp
....\.....\图10-25.bmp
....\.....\图10-28.bmp
....\.....\表10-3.bmp
....\work\zigzag
....\....\fdct
....\....\dctub
....\....\dctu
....\....\dct_testbench
....\....\dct_syn
....\....\dct_mac
....\....\dct
....\....\bench_top
....\work
....\wave
....\chart
10.3
....\dct.mpf
....\dct.v
....\dct_cos_table.v
....\dct_mac.v
....\dct_syn.v
....\dct_testbench.v
....\dctu.v
....\dctub.v
....\fdct.v
....\qnr.cr.mti
....\timescale.v
....\transcript
....\vsim.wlf
....\zigzag.v
....\work\_info
....\....\zigzag\_primary.dat
....\....\......\_primary.vhd
....\....\......\verilog.asm
....\....\fdct\_primary.dat
....\....\....\_primary.vhd
....\....\....\verilog.asm
....\....\dctub\_primary.dat
....\....\.....\_primary.vhd
....\....\.....\verilog.asm
....\....\....\_primary.dat
....\....\....\_primary.vhd
....\....\....\verilog.asm
....\....\..._testbench\_primary.dat
....\....\.............\_primary.vhd
....\....\.............\verilog.asm
....\....\....syn\_primary.dat
....\....\.......\_primary.vhd
....\....\.......\verilog.asm
....\....\....mac\_primary.dat
....\....\.......\_primary.vhd
....\....\.......\verilog.asm
....\....\...\_primary.dat
....\....\...\_primary.vhd
....\....\...\verilog.asm
....\....\bench_top\_primary.dat
....\....\.........\_primary.vhd
....\....\.........\verilog.asm
....\.ave\Thumbs.db
....\....\dct.bmp
....\....\dct_testbench.bmp
....\....\dctu.bmp
....\....\dctub.bmp
....\....\fdct.bmp
....\....\zigzag.bmp
....\chart\Thumbs.db
....\.....\图10-18.bmp
....\.....\图10-19.bmp
....\.....\图10-20.bmp
....\.....\图10-22.bmp
....\.....\图10-23.bmp
....\.....\图10-25.bmp
....\.....\图10-28.bmp
....\.....\表10-3.bmp
....\work\zigzag
....\....\fdct
....\....\dctub
....\....\dctu
....\....\dct_testbench
....\....\dct_syn
....\....\dct_mac
....\....\dct
....\....\bench_top
....\work
....\wave
....\chart
10.3