文件名称:my_clock
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使用verilog HDL语言编写的时钟电路代码，能实现24小时电子钟的功能。-Using verilog HDL code written in the clock circuit can achieve 24-hour clock function.
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下载文件列表
my_clock\counter10.v
........\counter10.v.bak
........\counter24.v
........\counter24.v.bak
........\counter6.v
........\counter6.v.bak
........\db\add_sub_fnh.tdf
........\..\add_sub_ooh.tdf
........\..\add_sub_poh.tdf
........\..\my_clock.asm.qmsg
........\..\my_clock.cbx.xml
........\..\my_clock.cmp.cdb
........\..\my_clock.cmp.hdb
........\..\my_clock.cmp.logdb
........\..\my_clock.cmp.rdb
........\..\my_clock.cmp.tdb
........\..\my_clock.cmp0.ddb
........\..\my_clock.dbp
........\..\my_clock.db_info
........\..\my_clock.eco.cdb
........\..\my_clock.eds_overflow
........\..\my_clock.fit.qmsg
........\..\my_clock.hier_info
........\..\my_clock.hif
........\..\my_clock.map.cdb
........\..\my_clock.map.hdb
........\..\my_clock.map.logdb
........\..\my_clock.map.qmsg
........\..\my_clock.pre_map.cdb
........\..\my_clock.pre_map.hdb
........\..\my_clock.psp
........\..\my_clock.pss
........\..\my_clock.rtlv.hdb
........\..\my_clock.rtlv_sg.cdb
........\..\my_clock.rtlv_sg_swap.cdb
........\..\my_clock.sgdiff.cdb
........\..\my_clock.sgdiff.hdb
........\..\my_clock.sim.cvwf
........\..\my_clock.sim.hdb
........\..\my_clock.sim.qmsg
........\..\my_clock.sim.rdb
........\..\my_clock.sld_design_entry.sci
........\..\my_clock.sld_design_entry_dsc.sci
........\..\my_clock.syn_hier_info
........\..\my_clock.tan.qmsg
........\..\my_clock.tis_db_list.ddb
........\..\prev_cmp_my_clock.asm.qmsg
........\..\prev_cmp_my_clock.fit.qmsg
........\..\prev_cmp_my_clock.map.qmsg
........\..\prev_cmp_my_clock.qmsg
........\..\prev_cmp_my_clock.sim.qmsg
........\..\prev_cmp_my_clock.tan.qmsg
........\..\wed.wsf
........\freq1000.v
........\freq1000.v.bak
........\my_clock.asm.rpt
........\my_clock.cdf
........\my_clock.done
........\my_clock.dpf
........\my_clock.fit.rpt
........\my_clock.fit.summary
........\my_clock.flow.rpt
........\my_clock.map.rpt
........\my_clock.map.summary
........\my_clock.pin
........\my_clock.pof
........\my_clock.qpf
........\my_clock.qsf
........\my_clock.qws
........\my_clock.sim.rpt
........\my_clock.sof
........\my_clock.tan.rpt
........\my_clock.tan.summary
........\my_clock.v
........\my_clock.vwf
........\db
my_clock
........\counter10.v.bak
........\counter24.v
........\counter24.v.bak
........\counter6.v
........\counter6.v.bak
........\db\add_sub_fnh.tdf
........\..\add_sub_ooh.tdf
........\..\add_sub_poh.tdf
........\..\my_clock.asm.qmsg
........\..\my_clock.cbx.xml
........\..\my_clock.cmp.cdb
........\..\my_clock.cmp.hdb
........\..\my_clock.cmp.logdb
........\..\my_clock.cmp.rdb
........\..\my_clock.cmp.tdb
........\..\my_clock.cmp0.ddb
........\..\my_clock.dbp
........\..\my_clock.db_info
........\..\my_clock.eco.cdb
........\..\my_clock.eds_overflow
........\..\my_clock.fit.qmsg
........\..\my_clock.hier_info
........\..\my_clock.hif
........\..\my_clock.map.cdb
........\..\my_clock.map.hdb
........\..\my_clock.map.logdb
........\..\my_clock.map.qmsg
........\..\my_clock.pre_map.cdb
........\..\my_clock.pre_map.hdb
........\..\my_clock.psp
........\..\my_clock.pss
........\..\my_clock.rtlv.hdb
........\..\my_clock.rtlv_sg.cdb
........\..\my_clock.rtlv_sg_swap.cdb
........\..\my_clock.sgdiff.cdb
........\..\my_clock.sgdiff.hdb
........\..\my_clock.sim.cvwf
........\..\my_clock.sim.hdb
........\..\my_clock.sim.qmsg
........\..\my_clock.sim.rdb
........\..\my_clock.sld_design_entry.sci
........\..\my_clock.sld_design_entry_dsc.sci
........\..\my_clock.syn_hier_info
........\..\my_clock.tan.qmsg
........\..\my_clock.tis_db_list.ddb
........\..\prev_cmp_my_clock.asm.qmsg
........\..\prev_cmp_my_clock.fit.qmsg
........\..\prev_cmp_my_clock.map.qmsg
........\..\prev_cmp_my_clock.qmsg
........\..\prev_cmp_my_clock.sim.qmsg
........\..\prev_cmp_my_clock.tan.qmsg
........\..\wed.wsf
........\freq1000.v
........\freq1000.v.bak
........\my_clock.asm.rpt
........\my_clock.cdf
........\my_clock.done
........\my_clock.dpf
........\my_clock.fit.rpt
........\my_clock.fit.summary
........\my_clock.flow.rpt
........\my_clock.map.rpt
........\my_clock.map.summary
........\my_clock.pin
........\my_clock.pof
........\my_clock.qpf
........\my_clock.qsf
........\my_clock.qws
........\my_clock.sim.rpt
........\my_clock.sof
........\my_clock.tan.rpt
........\my_clock.tan.summary
........\my_clock.v
........\my_clock.vwf
........\db
my_clock