文件名称:DDR_prj
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DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA。-DDR controller VHDL source code. FPGA implementation using DDR interface controller for Altera' s FPGA.
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下载文件列表
DDR_prj\db\ddr_sdram.asm.qmsg
.......\..\ddr_sdram.asm_labs.ddb
.......\..\ddr_sdram.cbx.xml
.......\..\ddr_sdram.cmp.bpm
.......\..\ddr_sdram.cmp.cdb
.......\..\ddr_sdram.cmp.ecobp
.......\..\ddr_sdram.cmp.hdb
.......\..\ddr_sdram.cmp.logdb
.......\..\ddr_sdram.cmp.rdb
.......\..\ddr_sdram.cmp_bb.cdb
.......\..\ddr_sdram.cmp_bb.hdb
.......\..\ddr_sdram.cmp_bb.logdb
.......\..\ddr_sdram.cmp_bb.rcf
.......\..\ddr_sdram.cuda_io_sim_cache.ff_0.hsd
.......\..\ddr_sdram.cuda_io_sim_cache.ss_85.hsd
.......\..\ddr_sdram.cuda_io_sim_cache.tt_85.hsd
.......\..\ddr_sdram.dbp
.......\..\ddr_sdram.db_info
.......\..\ddr_sdram.eco.cdb
.......\..\ddr_sdram.fit.qmsg
.......\..\ddr_sdram.hier_info
.......\..\ddr_sdram.hif
.......\..\ddr_sdram.map.bpm
.......\..\ddr_sdram.map.cdb
.......\..\ddr_sdram.map.ecobp
.......\..\ddr_sdram.map.hdb
.......\..\ddr_sdram.map.logdb
.......\..\ddr_sdram.map.qmsg
.......\..\ddr_sdram.map_bb.cdb
.......\..\ddr_sdram.map_bb.hdb
.......\..\ddr_sdram.map_bb.logdb
.......\..\ddr_sdram.merge_hb.atm
.......\..\ddr_sdram.pre_map.cdb
.......\..\ddr_sdram.pre_map.hdb
.......\..\ddr_sdram.psp
.......\..\ddr_sdram.pss
.......\..\ddr_sdram.rtlv.hdb
.......\..\ddr_sdram.rtlv_sg.cdb
.......\..\ddr_sdram.rtlv_sg_swap.cdb
.......\..\ddr_sdram.sgdiff.cdb
.......\..\ddr_sdram.sgdiff.hdb
.......\..\ddr_sdram.signalprobe.cdb
.......\..\ddr_sdram.sld_design_entry.sci
.......\..\ddr_sdram.sld_design_entry_dsc.sci
.......\..\ddr_sdram.sta.qmsg
.......\..\ddr_sdram.sta.rdb
.......\..\ddr_sdram.syn_hier_info
.......\..\ddr_sdram.tiscmp.fastest_slow_1200mv_0c.ddb
.......\..\ddr_sdram.tiscmp.fastest_slow_1200mv_85c.ddb
.......\..\ddr_sdram.tiscmp.fast_1200mv_0c.ddb
.......\..\ddr_sdram.tiscmp.slow_1200mv_0c.ddb
.......\..\ddr_sdram.tiscmp.slow_1200mv_85c.ddb
.......\..\ddr_sdram.tis_db_list.ddb
.......\..\prev_cmp_ddr_sdram.fit.qmsg
.......\..\prev_cmp_ddr_sdram.map.qmsg
.......\..\prev_cmp_ddr_sdram.qmsg
.......\ddr_command.vhd
.......\ddr_control_interface.vhd
.......\ddr_data_path.vhd
.......\ddr_sdram.asm.rpt
.......\ddr_sdram.done
.......\ddr_sdram.dpf
.......\ddr_sdram.fit.rpt
.......\ddr_sdram.fit.smsg
.......\ddr_sdram.fit.summary
.......\ddr_sdram.flow.rpt
.......\ddr_sdram.map.rpt
.......\ddr_sdram.map.summary
.......\ddr_sdram.pin
.......\ddr_sdram.pof
.......\ddr_sdram.qpf
.......\ddr_sdram.qsf
.......\ddr_sdram.sof
.......\ddr_sdram.sta.rpt
.......\ddr_sdram.sta.summary
.......\ddr_sdram.vhd
.......\ddr_sdram.vhd.bak
.......\pll1.ppf
.......\pll1.vhd
.......\pll1_wave0.jpg
.......\pll1_waveforms.html
.......\pll_all.vhd
.......\db
DDR_prj
.......\..\ddr_sdram.asm_labs.ddb
.......\..\ddr_sdram.cbx.xml
.......\..\ddr_sdram.cmp.bpm
.......\..\ddr_sdram.cmp.cdb
.......\..\ddr_sdram.cmp.ecobp
.......\..\ddr_sdram.cmp.hdb
.......\..\ddr_sdram.cmp.logdb
.......\..\ddr_sdram.cmp.rdb
.......\..\ddr_sdram.cmp_bb.cdb
.......\..\ddr_sdram.cmp_bb.hdb
.......\..\ddr_sdram.cmp_bb.logdb
.......\..\ddr_sdram.cmp_bb.rcf
.......\..\ddr_sdram.cuda_io_sim_cache.ff_0.hsd
.......\..\ddr_sdram.cuda_io_sim_cache.ss_85.hsd
.......\..\ddr_sdram.cuda_io_sim_cache.tt_85.hsd
.......\..\ddr_sdram.dbp
.......\..\ddr_sdram.db_info
.......\..\ddr_sdram.eco.cdb
.......\..\ddr_sdram.fit.qmsg
.......\..\ddr_sdram.hier_info
.......\..\ddr_sdram.hif
.......\..\ddr_sdram.map.bpm
.......\..\ddr_sdram.map.cdb
.......\..\ddr_sdram.map.ecobp
.......\..\ddr_sdram.map.hdb
.......\..\ddr_sdram.map.logdb
.......\..\ddr_sdram.map.qmsg
.......\..\ddr_sdram.map_bb.cdb
.......\..\ddr_sdram.map_bb.hdb
.......\..\ddr_sdram.map_bb.logdb
.......\..\ddr_sdram.merge_hb.atm
.......\..\ddr_sdram.pre_map.cdb
.......\..\ddr_sdram.pre_map.hdb
.......\..\ddr_sdram.psp
.......\..\ddr_sdram.pss
.......\..\ddr_sdram.rtlv.hdb
.......\..\ddr_sdram.rtlv_sg.cdb
.......\..\ddr_sdram.rtlv_sg_swap.cdb
.......\..\ddr_sdram.sgdiff.cdb
.......\..\ddr_sdram.sgdiff.hdb
.......\..\ddr_sdram.signalprobe.cdb
.......\..\ddr_sdram.sld_design_entry.sci
.......\..\ddr_sdram.sld_design_entry_dsc.sci
.......\..\ddr_sdram.sta.qmsg
.......\..\ddr_sdram.sta.rdb
.......\..\ddr_sdram.syn_hier_info
.......\..\ddr_sdram.tiscmp.fastest_slow_1200mv_0c.ddb
.......\..\ddr_sdram.tiscmp.fastest_slow_1200mv_85c.ddb
.......\..\ddr_sdram.tiscmp.fast_1200mv_0c.ddb
.......\..\ddr_sdram.tiscmp.slow_1200mv_0c.ddb
.......\..\ddr_sdram.tiscmp.slow_1200mv_85c.ddb
.......\..\ddr_sdram.tis_db_list.ddb
.......\..\prev_cmp_ddr_sdram.fit.qmsg
.......\..\prev_cmp_ddr_sdram.map.qmsg
.......\..\prev_cmp_ddr_sdram.qmsg
.......\ddr_command.vhd
.......\ddr_control_interface.vhd
.......\ddr_data_path.vhd
.......\ddr_sdram.asm.rpt
.......\ddr_sdram.done
.......\ddr_sdram.dpf
.......\ddr_sdram.fit.rpt
.......\ddr_sdram.fit.smsg
.......\ddr_sdram.fit.summary
.......\ddr_sdram.flow.rpt
.......\ddr_sdram.map.rpt
.......\ddr_sdram.map.summary
.......\ddr_sdram.pin
.......\ddr_sdram.pof
.......\ddr_sdram.qpf
.......\ddr_sdram.qsf
.......\ddr_sdram.sof
.......\ddr_sdram.sta.rpt
.......\ddr_sdram.sta.summary
.......\ddr_sdram.vhd
.......\ddr_sdram.vhd.bak
.......\pll1.ppf
.......\pll1.vhd
.......\pll1_wave0.jpg
.......\pll1_waveforms.html
.......\pll_all.vhd
.......\db
DDR_prj