文件名称:add
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自己用verilog写的加法器,时序仿真已经通过-Their own written with verilog adder, timing simulation has been adopted
(系统自动生成,下载前可以参看下载内容)
下载文件列表
add\Add.v
...\SerialReceive.v
...\serial_sent.v
add
...\SerialReceive.v
...\serial_sent.v
add