文件名称:add(FLP)
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一个32位元的浮点数加法器，可将两IEEE 754格式内的值进行相加-A 32-bit floating-point adder can be both within the IEEE 754 format to add value
相关搜索： vhdl
32
bit
adder
floating
point
adder
floating
floating
point
adder
ieee
754
浮点数加法
VHDL
加法器
add
floating
point
floating
point
vhdl
ieee
exponential
vhdl
adder
754
754
add
32
bit
adder
floating
point
adder
floating
floating
point
adder
ieee
754
浮点数加法
VHDL
加法器
add
floating
point
floating
point
vhdl
ieee
exponential
vhdl
adder
754
754
add
(系统自动生成,下载前可以参看下载内容)
下载文件列表
add(FLP)
........\architecture.txt
........\fpadd_32.vhd
........\fpadd_32tb.v
........\fpadd_normalize.vhd
........\fpalign.vhd
........\fpinvert.vhd
........\fplzc.vhd
........\fpnormalize.vhd
........\fpround.vhd
........\fpselcomplement.vhd
........\fpswap.vhd
........\packfp.vhd
........\transcript
........\unpackfp.vhd
........\vish_stacktrace.vstf
........\architecture.txt
........\fpadd_32.vhd
........\fpadd_32tb.v
........\fpadd_normalize.vhd
........\fpalign.vhd
........\fpinvert.vhd
........\fplzc.vhd
........\fpnormalize.vhd
........\fpround.vhd
........\fpselcomplement.vhd
........\fpswap.vhd
........\packfp.vhd
........\transcript
........\unpackfp.vhd
........\vish_stacktrace.vstf