文件名称:PWM_GEN

  • 所属分类:
  • 其他小程序
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 245kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 洛**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

这是Altera PWM生成的一个实例。包含project文件,源代码,仿真文件。经过验证,实际可用。-This is an example of Altera PWM generated. Contains the project files, source code, simulation files. After verification, the actual available.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Pulse_gen\code\pwm_main.v

.........\modelsim\pulse_width_modulator.cr.mti

.........\........\pulse_width_modulator.mpf

.........\........\pwm_main.v

.........\........\pwm_sim.cr.mti

.........\........\pwm_sim.mpf

.........\........\test_pwm.v

.........\........\wave.bmp

.........\........\wave.do

.........\........\wave2.bmp

.........\........\wave2.do

.........\........\wave3.bmp

.........\........\wave3.do

.........\........\wave4.bmp

.........\........\wave4.do

.........\........\wave5.bmp

.........\........\wave5.do

.........\........\.ork\altufm_osc0_altufm_osc_1p3\verilog.asm

.........\........\....\..........................\_primary.dat

.........\........\....\..........................\_primary.vhd

.........\........\....\clkgen\verilog.asm

.........\........\....\......\_primary.dat

.........\........\....\......\_primary.vhd

.........\........\....\..._gen\verilog.asm

.........\........\....\.......\_primary.dat

.........\........\....\.......\_primary.vhd

.........\........\....\dutycycle\verilog.asm

.........\........\....\.........\_primary.dat

.........\........\....\.........\_primary.vhd

.........\........\....\...._cycle\verilog.asm

.........\........\....\..........\_primary.dat

.........\........\....\..........\_primary.vhd

.........\........\....\pwm_gen\verilog.asm

.........\........\....\.......\_primary.dat

.........\........\....\.......\_primary.vhd

.........\........\....\....main\verilog.asm

.........\........\....\........\_primary.dat

.........\........\....\........\_primary.vhd

.........\........\....\test_pwm\verilog.asm

.........\........\....\........\_primary.dat

.........\........\....\........\_primary.vhd

.........\........\....\_info

.........\quartus\db\pwm_main.asm.qmsg

.........\.......\..\pwm_main.asm_labs.ddb

.........\.......\..\pwm_main.cbx.xml

.........\.......\..\pwm_main.cmp.cdb

.........\.......\..\pwm_main.cmp.hdb

.........\.......\..\pwm_main.cmp.logdb

.........\.......\..\pwm_main.cmp.rdb

.........\.......\..\pwm_main.cmp.tdb

.........\.......\..\pwm_main.cmp0.ddb

.........\.......\..\pwm_main.dbp

.........\.......\..\pwm_main.db_info

.........\.......\..\pwm_main.eco.cdb

.........\.......\..\pwm_main.fit.qmsg

.........\.......\..\pwm_main.hier_info

.........\.......\..\pwm_main.hif

.........\.......\..\pwm_main.map.cdb

.........\.......\..\pwm_main.map.hdb

.........\.......\..\pwm_main.map.logdb

.........\.......\..\pwm_main.map.qmsg

.........\.......\..\pwm_main.pre_map.cdb

.........\.......\..\pwm_main.pre_map.hdb

.........\.......\..\pwm_main.psp

.........\.......\..\pwm_main.pss

.........\.......\..\pwm_main.rtlv.hdb

.........\.......\..\pwm_main.rtlv_sg.cdb

.........\.......\..\pwm_main.rtlv_sg_swap.cdb

.........\.......\..\pwm_main.sgdiff.cdb

.........\.......\..\pwm_main.sgdiff.hdb

.........\.......\..\pwm_main.signalprobe.cdb

.........\.......\..\pwm_main.sld_design_entry.sci

.........\.......\..\pwm_main.sld_design_entry_dsc.sci

.........\.......\..\pwm_main.syn_hier_info

.........\.......\..\pwm_main.tan.qmsg

.........\.......\..\pwm_main.tis_db_list.ddb

.........\.......\pwm_main.asm.rpt

.........\.......\pwm_main.cdf

.........\.......\pwm_main.done

.........\.......\pwm_main.dpf

.........\.......\pwm_main.fit.rpt

.........\.......\pwm_main.fit.smsg

.........\.......\pwm_main.fit.summary

.........\.......\pwm_main.flow.rpt

.........\.......\pwm_main.map.rpt

.........\.......\pwm_main.map.summary

.........\.......\pwm_main.pin

.........\.......\pwm_main.pof

.........\.......\pwm_main.qpf

.........\.......\pwm_main.qsf

.........\.......\pwm_main.qws

.........\.......\pwm_main.tan.rpt

.........\.......\pwm_main.v

.........\.......\pwm_main_assignment_defaults.qdf

.........\testbench\test_pwm.v

.........\modelsim\work\altufm_osc0_altufm_osc_1p3

.........\........\....\clkgen

.........\........\....\clk_gen

.........\........\....\dutycycle

.........\........\....\duty_cycle

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