文件名称:dds_final

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 1.56mb
  • 下载次数:
  • 1次
  • 提 供 者:
  • nost*****
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

使用Verilog HDL语言实现的一个DDS,可以发生0-10Mhz正弦波、方波、三角波,频率步进可调,FM调制、AM调制,调制度可调。DA芯片为8位并行,160MHz-Using the Verilog HDL language implementation of a DDS, can occur 0-10Mhz sine, square, triangle wave, frequency step tunable, FM modulation, AM modulation, adjustable modulation. DA-chip 8-bit parallel, 160MHz
(系统自动生成,下载前可以参看下载内容)

下载文件列表

dds_final\AM_data.bsf

.........\AM_data.v

.........\AM_data.v.bak

.........\AM_mult.bsf

.........\AM_mult.qip

.........\AM_mult.v

.........\AM_mult_bb.v

.........\AM_mult_wave0.jpg

.........\AM_mult_waveforms.html

.........\contrl.bsf

.........\contrl.v

.........\contrl.v.bak

.........\db\altsyncram_8f91.tdf

.........\..\altsyncram_ss91.tdf

.........\..\dds_final.asm.qmsg

.........\..\dds_final.atom.rvd

.........\..\dds_final.atom_map.rvd

.........\..\dds_final.cbx.xml

.........\..\dds_final.cmp.ecobp

.........\..\dds_final.cmp.rdb

.........\..\dds_final.cmp0.ddb

.........\..\dds_final.cmp2.ddb

.........\..\dds_final.db_info

.........\..\dds_final.eco.cdb

.........\..\dds_final.eda.qmsg

.........\..\dds_final.eds_overflow

.........\..\dds_final.fit.qmsg

.........\..\dds_final.fnsim.cdb

.........\..\dds_final.fnsim.hdb

.........\..\dds_final.fnsim.qmsg

.........\..\dds_final.hier_info

.........\..\dds_final.hif

.........\..\dds_final.map.bpm

.........\..\dds_final.map.cdb

.........\..\dds_final.map.ecobp

.........\..\dds_final.map.hdb

.........\..\dds_final.map.logdb

.........\..\dds_final.map.qmsg

.........\..\dds_final.map_bb.cdb

.........\..\dds_final.map_bb.hdb

.........\..\dds_final.map_bb.hdbx

.........\..\dds_final.map_bb.logdb

.........\..\dds_final.pre_map.cdb

.........\..\dds_final.pre_map.hdb

.........\..\dds_final.psp

.........\..\dds_final.root_partition.cmp.atm

.........\..\dds_final.root_partition.cmp.cfm

.........\..\dds_final.root_partition.cmp.dfp

.........\..\dds_final.root_partition.cmp.hdbx

.........\..\dds_final.root_partition.cmp.logdb

.........\..\dds_final.root_partition.cmp.rcf

.........\..\dds_final.root_partition.map.atm

.........\..\dds_final.root_partition.map.hdbx

.........\..\dds_final.root_partition.map.info

.........\..\dds_final.root_partition.merge_hb.atm

.........\..\dds_final.rpp.qmsg

.........\..\dds_final.rtlv.hdb

.........\..\dds_final.rtlv_sg.cdb

.........\..\dds_final.rtlv_sg_swap.cdb

.........\..\dds_final.sgate.rvd

.........\..\dds_final.sgate_sm.rvd

.........\..\dds_final.sgdiff.cdb

.........\..\dds_final.sgdiff.hdb

.........\..\dds_final.sim.cvwf

.........\..\dds_final.sim.hdb

.........\..\dds_final.sim.qmsg

.........\..\dds_final.sim.rdb

.........\..\dds_final.simfam

.........\..\dds_final.sld_design_entry.sci

.........\..\dds_final.sld_design_entry_dsc.sci

.........\..\dds_final.syn_hier_info

.........\..\dds_final.tan.qmsg

.........\..\dds_final.tis_db_list.ddb

.........\..\mult_71n.tdf

.........\..\mult_91n.tdf

.........\..\mult_f2n.tdf

.........\..\mult_m2n.tdf

.........\..\mult_p2n.tdf

.........\..\mult_r2n.tdf

.........\..\prev_cmp_dds_final.asm.qmsg

.........\..\prev_cmp_dds_final.eda.qmsg

.........\..\prev_cmp_dds_final.fit.qmsg

.........\..\prev_cmp_dds_final.map.qmsg

.........\..\prev_cmp_dds_final.qmsg

.........\..\prev_cmp_dds_final.sim.qmsg

.........\..\prev_cmp_dds_final.tan.qmsg

.........\..\wed.wsf

.........\dds_ctrl.bsf

.........\dds_ctrl.v

.........\dds_ctrl.v.bak

.........\dds_final.asm.rpt

.........\dds_final.bdf

.........\dds_final.bsf

.........\dds_final.done

.........\dds_final.eda.rpt

.........\dds_final.fit.rpt

.........\dds_final.fit.smsg

.........\dds_final.fit.summary

.........\dds_final.flow.rpt

.........\dds_final.hexout

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