文件名称:fft_gen
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FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results.
here is what I do:
1- from core generator I choose fft core and create .vhd & .vho & .xco files.
2- I add the .xco & .vhd files to my project.
3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.-FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results.
here is what I do:
1- from core generator I choose fft core and create .vhd & .vho & .xco files.
2- I add the .xco & .vhd files to my project.
3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.
here is what I do:
1- from core generator I choose fft core and create .vhd & .vho & .xco files.
2- I add the .xco & .vhd files to my project.
3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.-FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results.
here is what I do:
1- from core generator I choose fft core and create .vhd & .vho & .xco files.
2- I add the .xco & .vhd files to my project.
3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.
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下载文件列表
fft_gen.doc