文件名称:uart-IP-Core
介绍说明－－下载内容均来自于网络，请自行研究使用
串口的FPGA VHDL的IP核 可以直接调用使用-Serial FPGA VHDL IP core can be called directly use
(系统自动生成,下载前可以参看下载内容)
下载文件列表
uart IP Core
............\bench
............\.....\CVS
............\.....\...\Entries
............\.....\...\Repository
............\.....\...\Root
............\.....\verilog
............\.....\.......\CVS
............\.....\.......\...\Entries
............\.....\.......\...\Repository
............\.....\.......\...\Root
............\.....\.......\readme.txt
............\.....\.......\test_cases
............\.....\.......\..........\CVS
............\.....\.......\..........\...\Entries
............\.....\.......\..........\...\Repository
............\.....\.......\..........\...\Root
............\.....\.......\..........\uart_int.v
............\.....\.......\uart_device.v
............\.....\.......\uart_device_utilities.v
............\.....\.......\uart_log.v
............\.....\.......\uart_test.v
............\.....\.......\uart_testbench.v
............\.....\.......\uart_testbench_defines.v
............\.....\.......\uart_testbench_utilities.v
............\.....\.......\uart_wb_utilities.v
............\.....\.......\vapi.log
............\.....\.......\wb_mast.v
............\.....\.......\wb_master_model.v
............\.....\.......\wb_model_defines.v
............\.....\vhdl
............\.....\....\.keepme
............\.....\....\CVS
............\.....\....\...\Entries
............\.....\....\...\Repository
............\.....\....\...\Root
............\CVS
............\...\Entries
............\...\Repository
............\...\Root
............\Doc
............\...\CHANGES.txt
............\...\CVS
............\...\...\Entries
............\...\...\Repository
............\...\...\Root
............\...\src
............\...\...\CVS
............\...\...\...\Entries
............\...\...\...\Repository
............\...\...\...\Root
............\...\...\UART_spec.doc
............\...\UART_spec.pdf
............\fv
............\..\.keepme
............\..\CVS
............\..\...\Entries
............\..\...\Repository
............\..\...\Root
............\lint
............\....\bin
............\....\...\.keepme
............\....\...\CVS
............\....\...\...\Entries
............\....\...\...\Repository
............\....\...\...\Root
............\....\CVS
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............\....\...\Repository
............\....\...\Root
............\....\log
............\....\...\.keepme
............\....\...\CVS
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............\....\...\...\Repository
............\....\...\...\Root
............\....\out
............\....\...\.keepme
............\....\...\CVS
............\....\...\...\Entries
............\....\...\...\Repository
............\....\...\...\Root
............\....\run
............\....\...\.keepme
............\....\...\CVS
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............\....\...\...\Repository
............\....\...\...\Root
............\rtl
............\...\CVS
............\...\...\Entries
............\...\...\Repository
............\...\...\Root
............\...\verilog
............\...\verilog-backup
............\...\..............\CVS
............\...\..............\...\Entries
............\...\..............\...\Repository
............\...\..............\...\Root
............\...\..............\timescale.v