文件名称:TimingConstraint

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 1.28mb
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  • 0次
  • 提 供 者:
  • j***
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xilinx公司提供的关于FPGA硬件设计的额时序约束参考资料-xilinx provided on the FPGA hardware design timing constraints of the amount of reference material
相关搜索: 时序约束

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下载文件列表

时序约束教程

............\blockram

............\........\readme_blockram_verilog.txt

............\........\verilog

............\........\.......\SelectRAM_A1.v

............\........\.......\SelectRAM_A18.v

............\........\.......\SelectRAM_A18_B18.v

............\........\.......\SelectRAM_A18_B36.v

............\........\.......\SelectRAM_A1_B1.v

............\........\.......\SelectRAM_A1_B18.v

............\........\.......\SelectRAM_A1_B2.v

............\........\.......\SelectRAM_A1_B36.v

............\........\.......\SelectRAM_A1_B4.v

............\........\.......\SelectRAM_A1_B9.v

............\........\.......\SelectRAM_A2.v

............\........\.......\SelectRAM_A2_B18.v

............\........\.......\SelectRAM_A2_B2.v

............\........\.......\SelectRAM_A2_B36.v

............\........\.......\SelectRAM_A2_B4.v

............\........\.......\SelectRAM_A2_B9.v

............\........\.......\SelectRAM_A36.v

............\........\.......\SelectRAM_A36_B36.v

............\........\.......\SelectRAM_A4.v

............\........\.......\SelectRAM_A4_B18.v

............\........\.......\SelectRAM_A4_B36.v

............\........\.......\SelectRAM_A4_B4.v

............\........\.......\SelectRAM_A4_B9.v

............\........\.......\SelectRAM_A9.v

............\........\.......\SelectRAM_A9_B18.v

............\........\.......\SelectRAM_A9_B36.v

............\........\.......\SelectRAM_A9_B9.v

............\........\.......\XC2V_RAMB_1_PORT.v

............\clock

............\.....\readme_clock_verilog.txt

............\.....\verilog

............\.....\.......\BUFGCE_1_SUBM.v

............\.....\.......\BUFGCE_SUBM.v

............\.....\.......\BUFGMUX_1_INST.v

............\.....\.......\BUFGMUX_INST.v

............\dcm

............\...\readme_dcm_verilog.txt

............\...\verilog

............\...\.......\BUFG_CLK0_FB_SUBM.v

............\...\.......\BUFG_CLK0_SUBM.v

............\...\.......\BUFG_CLK2X_FB_SUBM.v

............\...\.......\BUFG_CLK2X_SUBM.v

............\...\.......\BUFG_CLKDV_SUBM.v

............\...\.......\BUFG_DFS_FB_SUBM.v

............\...\.......\BUFG_DFS_SUBM.v

............\...\.......\BUFG_PHASE_CLK0_SUBM.v

............\...\.......\BUFG_PHASE_CLK2X_SUBM.v

............\...\.......\BUFG_PHASE_CLKDV_SUBM.v

............\...\.......\BUFG_PHASE_CLKFX_FB_SUBM.v

............\...\.......\DCM_INST.v

............\ddr

............\...\readme_ddr_verilog.txt

............\...\verilog

............\...\.......\DDR_3state.v

............\...\.......\DDR_Input.v

............\...\.......\DDR_Output.v

............\distributed_ram

............\...............\readme_distributed_ram_verilog.txt

............\...............\verilog

............\...............\.......\SelectRAM_128S.v

............\...............\.......\SelectRAM_16D.v

............\...............\.......\SelectRAM_16S.v

............\...............\.......\SelectRAM_32D.v

............\...............\.......\SelectRAM_32S.v

............\...............\.......\SelectRAM_64D.v

............\...............\.......\SelectRAM_64S.v

............\...............\.......\XC2V_DISTRI_RAM_64S.v

............\...............\.......\XC2V_RAM128XN_S.v

............\...............\.......\XC2V_RAM16XN_D.v

............\...............\.......\XC2V_RAM16XN_S.v

............\...............\.......\XC2V_RAM32XN_D.v

............\...............\.......\XC2V_RAM32XN_S.v

............\...............\.......\XC2V_RAM64XN_D.v

............\...............\.......\XC2V_RAM64XN_S.v

............\lvds

............\....\readme_lvds_verilog.txt

............\....\verilog

............\....\.......\DDR_LVDS_3STATE.v

............\....\.......\DDR_LVDS_IN.v

............\....\.......\DDR_LVDS_OUT.v

............\multiplexers

............\............\readme_multiplexers_verilog.txt

............\............\verilog

............\............\.......\MUX_16_1.v

............\............\.......\MUX_2_1.v

............\............\.......\MUX_32_1.v

............\............\.......\MUX_4_1.v

............\............\.......\MUX_8_1.v

............\multipliers

............\...........\readme_multipliers_ver

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