文件名称:Processor_alu
- 所属分类：
- VHDL编程
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 4kb
- 下载次数：
- 0次
- 提 供 者：
- Yogesh******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
this Code is in verilog HDL.
This Code is for piplined processor with 4 opcode.
this will work in three cycle latch, decode and exicute..
test bench for xilinx ise is laos given
This Code is for piplined processor with 4 opcode.
this will work in three cycle latch, decode and exicute..
test bench for xilinx ise is laos given
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下载文件列表
Processor_alu
.............\alu_top.v
.............\alu_control_tbw.tfw
.............\IF_alu.v
.............\DC_alu.v
.............\EX_alu.v
.............\alu_control.v
.............\alu_top.v
.............\alu_control_tbw.tfw
.............\IF_alu.v
.............\DC_alu.v
.............\EX_alu.v
.............\alu_control.v