cp_moni1

........\beipin.v

........\db

........\..\fpga1.asm.qmsg

........\..\fpga1.cbx.xml

........\..\fpga1.cmp.cdb

........\..\fpga1.cmp.hdb

........\..\fpga1.cmp.qrpt

........\..\fpga1.cmp.rdb

........\..\fpga1.cmp.tdb

........\..\fpga1.cmp0.ddb

........\..\fpga1.dbp

........\..\fpga1.db_info

........\..\fpga1.eco.cdb

........\..\fpga1.eds_overflow

........\..\fpga1.fit.qmsg

........\..\fpga1.hier_info

........\..\fpga1.hif

........\..\fpga1.map.cdb

........\..\fpga1.map.hdb

........\..\fpga1.map.qmsg

........\..\fpga1.pre_map.cdb

........\..\fpga1.pre_map.hdb

........\..\fpga1.psp

........\..\fpga1.rtlv.hdb

........\..\fpga1.rtlv_sg.cdb

........\..\fpga1.rtlv_sg_swap.cdb

........\..\fpga1.sgdiff.cdb

........\..\fpga1.sgdiff.hdb

........\..\fpga1.signalprobe.cdb

........\..\fpga1.sim.hdb

........\..\fpga1.sim.qmsg

........\..\fpga1.sim.qrpt

........\..\fpga1.sim.rdb

........\..\fpga1.sim.vwf

........\..\fpga1.sld_design_entry.sci

........\..\fpga1.sld_design_entry_dsc.sci

........\..\fpga1.syn_hier_info

........\..\fpga1.tan.qmsg

........\fpga1.asm.rpt

........\fpga1.done

........\fpga1.fit.eqn

........\fpga1.fit.rpt

........\fpga1.fit.summary

........\fpga1.flow.rpt

........\fpga1.map.eqn

........\fpga1.map.rpt

........\fpga1.map.summary

........\fpga1.pin

........\fpga1.pof

........\fpga1.qpf

........\fpga1.qsf

........\fpga1.qws

........\fpga1.sim.rpt

........\fpga1.sof

........\fpga1.tan.rpt

........\fpga1.tan.summary

........\fpga1.v

........\fpga1.vwf

........\serv_req_info.txt