文件名称:FIR
- 所属分类:
- VHDL编程
- 资源属性:
- 上传时间:
- 2012-11-26
- 文件大小:
- 1kb
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- 0次
- 提 供 者:
- dhana*****
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The first three examples illustrate the difference between RTL FSMD model (Finite State Machine with Datapath buildin) and RTL FSM + DataPath model. From view of RT level design, each digital design consists of a Control Unit (FSM) and a Datapath. The datapath consists of storage units such as registers and memories, and combinational units such as ALUs, adders, multipliers, shifters, and comparators.
相关搜索: multipliers
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FIR\FIR.vhd
FIR
FIR