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booth_mul
- 一种可以完成16位有符号／无符号二进制数乘法的乘法器。该乘法器采用了改进的Booth算法，简化了部分积的符号扩展，采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元，整个设计用VHDL语言实现。-a 16 to be completed with symbols / unsigned multiplication of the number of binary multiplier
multipliers
- 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
VHDL_Development_Board_Sources
- 这是我最近买的一套CPLD开发板VHDL源程序并附上开发板的原理图,希望对你是一个很好的帮助!其中内容为:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟.-which I have recently bought a CPLD Development Board VHDL source cod
and1
- 用VHDL语言编写的三位二进制的乘法器，其原理是每位相乘后再错位相加-using VHDL prepared by the three binary multipliers, the principle is that each subsequent dislocation multiplication sum
Verilog_Development_Board_Sources
- 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Develo
4mult
- 可用的4位乘法器，用VHDL在FPGA中实现-available four multipliers, FPGA VHDL in achieving
MutiplierDesign
- 流水线乘法器,vhdl语言描述, 希望对大家有所帮助 -pipelined multipliers, vhdl language, we hope to help
changyongdevhdl
- 4位乘法器,4位除法器 8位数据锁存器,8位相等比较器,带同步复位的状态 机,元件例化与层次设计,最高优先级编码器-four multipliers, dividers four eight data latches, and eight other phase comparators, synchronous reset with the state machine, the component level with the
4mult
- 可用的4位乘法器，用VHDL在FPGA中实现-available four multipliers, FPGA VHDL in achieving
mul8
- ieee公布的标准8位浮点乘法器，可综合。采用标准算法。-ieee the standards published by the eight floating-point multipliers, can be integrated. The use of standard algorithm.
applicationofhardwaredescripptionlanguageCVHDLinth
- 通过四位乘法器的实例详细介绍了用ＶＨＤＬ语言设计数字系统的流程和方法，通过仿真实现预定目的．-Through the four examples of multipliers detailed design using VHDL language digital system processes and methods, through the simulation to achieve the intended purpose.
mul(FLP)
- 一个32位元的浮点数乘法器，可将两IEEE 754格式的值进行相乘-A 32-bit floating-point multipliers, can be two format IEEE 754 values multiplied
0
- 用vhdl语言实现4位乘法器，已被测试过，可参考使用-Vhdl language with four multipliers, have been tested, may refer to the use of
VHDL
- VHDL对各种电路的基本实现，包括乘法器，触发器，加减法器等-VHDL for the basic realization of the various circuits, including multipliers, flip-flops, and other instruments used in addition and subtraction
FIR
- The first three examples illustrate the difference between RTL FSMD model (Finite State Machine with Datapath buildin) and RTL FSM + DataPath model. From view of RT level design, each digital design consists of a Control
34105908-Multipliers-Using-Vhdl
- ABSTRACT: Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major d
Four-multipliers-with-VHDL-
- 用VHDL实现四位乘法器，不直接用乘法实现。该代码思路清晰，希望可以帮助到大家！-Four multipliers with VHDL implementation, not directly with the multiplication implementation. The code is clear thinking, I hope to help to you!
8-Multipliers
- 国外大学上课用PPT。关于乘法器架构，实现，优化，有booth算法的具体实例。-Foreign university classes PPT. About multipliers architecture, implementation, optimization, there is a specific instance of the booth algorithm.
Lagrange-multipliers
- 在matlab的环境下实现拉格朗日乘子法 -matlab achieve Lagrange multipliers
Multipliers
- 各种乘法器，不同算法类型的，适用于不同情况。(Various multipliers, different algorithmic types, are applied to different situations.)