文件名称:oscillograph
介绍说明－－下载内容均来自于网络，请自行研究使用
用VHDL编写的oscillograph数字部分源代码，在Altera FPGA上跑通。直接把模拟部分输入输出AD，DA信号接入本模块即可。-Digital oscillograph with the written part of the VHDL source code, in the Altera FPGA on the run-pass. Directly to the analog input and output AD, DA signal can access this module.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
DAx_module.vhd
DAy_module.vhd
mySPI_receive_top.vhd
osc_top.vhd
PCMP.vhd
pll_20.vhd
ram_2port.vhd
ram_3port.vhd
Ram_rclk.vhd
ReadRam_module.vhd
sipo.vhd
tri_module.vhd
WriteRam_module.vhd
clk_control.vhd
clk_div2.vhd
DAy_module.vhd
mySPI_receive_top.vhd
osc_top.vhd
PCMP.vhd
pll_20.vhd
ram_2port.vhd
ram_3port.vhd
Ram_rclk.vhd
ReadRam_module.vhd
sipo.vhd
tri_module.vhd
WriteRam_module.vhd
clk_control.vhd
clk_div2.vhd