文件名称:USB2.0InterfaceDesign

  • 所属分类:
  • 其他小程序
  • 资源属性:
  • [Windows] [Visual C] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 3.41mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • w***
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USB2.0接口的实现,包括VC驱动程序-USB2.0 interface implementation, including the VC drivers
相关搜索: wr_fifo
sof

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下载文件列表

USB2.0接口的设计与实现\slave fifo说明文档.doc

......................\写FIFO\Apptest\ezusbsys.h

......................\......\.......\ReadMe.txt

......................\......\.......\..lease\StdAfx.obj

......................\......\.......\.......\Test.exe

......................\......\.......\.......\Test.obj

......................\......\.......\.......\Test.res

......................\......\.......\.......\TestDlg.obj

......................\......\.......\.......\vc60.idb

......................\......\.......\res\cursor1.cur

......................\......\.......\...\icon5.ico

......................\......\.......\...\Test.ico

......................\......\.......\...\Test.rc2

......................\......\.......\...\usb.ico

......................\......\.......\Resource.h

......................\......\.......\StdAfx.cpp

......................\......\.......\StdAfx.h

......................\......\.......\Test.aps

......................\......\.......\Test.clw

......................\......\.......\Test.cpp

......................\......\.......\Test.dsp

......................\......\.......\Test.dsw

......................\......\.......\Test.h

......................\......\.......\Test.ncb

......................\......\.......\Test.opt

......................\......\.......\Test.plg

......................\......\.......\Test.rc

......................\......\.......\TestDlg.cpp

......................\......\.......\TestDlg.h

......................\......\wr_fifo\cmp_state.ini

......................\......\.......\db\cntr_l18.tdf

......................\......\.......\..\cntr_n28.tdf

......................\......\.......\..\wr_fifo.asm.qmsg

......................\......\.......\..\wr_fifo.cbx.xml

......................\......\.......\..\wr_fifo.cmp.cdb

......................\......\.......\..\wr_fifo.cmp.hdb

......................\......\.......\..\wr_fifo.cmp.rdb

......................\......\.......\..\wr_fifo.cmp.tdb

......................\......\.......\..\wr_fifo.cmp0.ddb

......................\......\.......\..\wr_fifo.db_info

......................\......\.......\..\wr_fifo.eco.cdb

......................\......\.......\..\wr_fifo.fit.qmsg

......................\......\.......\..\wr_fifo.hier_info

......................\......\.......\..\wr_fifo.hif

......................\......\.......\..\wr_fifo.map.cdb

......................\......\.......\..\wr_fifo.map.hdb

......................\......\.......\..\wr_fifo.map.qmsg

......................\......\.......\..\wr_fifo.pre_map.cdb

......................\......\.......\..\wr_fifo.pre_map.hdb

......................\......\.......\..\wr_fifo.psp

......................\......\.......\..\wr_fifo.rtlv.hdb

......................\......\.......\..\wr_fifo.rtlv_sg.cdb

......................\......\.......\..\wr_fifo.rtlv_sg_swap.cdb

......................\......\.......\..\wr_fifo.sgdiff.cdb

......................\......\.......\..\wr_fifo.sgdiff.hdb

......................\......\.......\..\wr_fifo.signalprobe.cdb

......................\......\.......\..\wr_fifo.sld_design_entry.sci

......................\......\.......\..\wr_fifo.sld_design_entry_dsc.sci

......................\......\.......\..\wr_fifo.smp_dump.txt

......................\......\.......\..\wr_fifo.syn_hier_info

......................\......\.......\..\wr_fifo.tan.qmsg

......................\......\.......\..\wr_fifo_cmp.qrpt

......................\......\.......\transcript

......................\......\.......\vish_stacktrace.vstf

......................\......\.......\vsim.wlf

......................\......\.......\work\wr_fifo\verilog.asm

......................\......\.......\....\.......\_primary.dat

......................\......\.......\....\.......\_primary.vhd

......................\......\.......\....\......._tb\verilog.asm

......................\......\.......\....\..........\_primary.dat

......................\......\.......\....\..........\_primary.vhd

......................\......\.......\....\_info

......................\......\.......\wr_fifo.asm.rpt

......................\......\.......\wr_fifo.cdf

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