文件名称:USB2.0IP_core_Verilog
介绍说明－－下载内容均来自于网络，请自行研究使用
完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-complete with verilog language development USB2.0 IP source code, including documentation, Simulation documents
相关搜索： USB2
0IP_core_Verilog
USB
verilog
verilog
USB
usb
ip
core
IP核
usb2
IP
core
usb2
0原理与工程开发
usb
core
0IP_core_Verilog
USB
verilog
verilog
USB
usb
ip
core
IP核
usb2
IP
core
usb2
0原理与工程开发
usb
core
(系统自动生成,下载前可以参看下载内容)
下载文件列表
USB2.0的IP核，包含文档和Verilog源码
...................................\usb_funct
...................................\.........\bench
...................................\.........\.....\CVS
...................................\.........\.....\...\Entries
...................................\.........\.....\...\Repository
...................................\.........\.....\...\Root
...................................\.........\.....\verilog
...................................\.........\.....\.......\CVS
...................................\.........\.....\.......\...\Entries
...................................\.........\.....\.......\...\Repository
...................................\.........\.....\.......\...\Root
...................................\.........\doc
...................................\.........\...\CVS
...................................\.........\...\...\Entries
...................................\.........\...\...\Repository
...................................\.........\...\...\Root
...................................\.........\...\README.txt
...................................\.........\...\STATUS.txt
...................................\.........\...\usb_doc.pdf
...................................\.........\rtl
...................................\.........\...\CVS
...................................\.........\...\...\Entries
...................................\.........\...\...\Repository
...................................\.........\...\...\Root
...................................\.........\...\verilog
...................................\.........\...\.......\CVS
...................................\.........\...\.......\...\Entries
...................................\.........\...\.......\...\Repository
...................................\.........\...\.......\...\Root
...................................\.........\...\.......\usbf_crc16.v
...................................\.........\...\.......\usbf_crc5.v
...................................\.........\...\.......\usbf_defines.v
...................................\.........\...\.......\usbf_ep_rf.v
...................................\.........\...\.......\usbf_ep_rf_dummy.v
...................................\.........\...\.......\usbf_idma.v
...................................\.........\...\.......\usbf_mem_arb.v
...................................\.........\...\.......\usbf_pa.v
...................................\.........\...\.......\usbf_pd.v
...................................\.........\...\.......\usbf_pe.v
...................................\.........\...\.......\usbf_pl.v
...................................\.........\...\.......\usbf_rf.v
...................................\.........\...\.......\usbf_top.v
...................................\.........\...\.......\usbf_utmi_if.v
...................................\.........\...\.......\usbf_utmi_ls.v
...................................\.........\...\.......\usbf_wb.v
...................................\.........\sim
...................................\.........\...\CVS
...................................\.........\...\...\Entries
...................................\.........\...\...\Repository
...................................\.........\...\...\Root
...................................\.........\...\rtl_sim
...................................\.........\...\.......\bin
...................................\.........\...\.......\...\CVS
...................................\.........\...\.......\...\...\Entries
...................................\.........\...\.......\...\...\Repository
...................................\.........\...\.......\...\...\Root
...................................\.........\...\.......\CVS
...................................\.........\...\.......\...\Entries
...................................\.........\...\.......\...\Repository
...................................\.........\...\.......\...\Root
...................................\.........\...\.......\run
...................................\.........\...\.......\...\CVS
...................................\.........\...\....
...................................\usb_funct
...................................\.........\bench
...................................\.........\.....\CVS
...................................\.........\.....\...\Entries
...................................\.........\.....\...\Repository
...................................\.........\.....\...\Root
...................................\.........\.....\verilog
...................................\.........\.....\.......\CVS
...................................\.........\.....\.......\...\Entries
...................................\.........\.....\.......\...\Repository
...................................\.........\.....\.......\...\Root
...................................\.........\doc
...................................\.........\...\CVS
...................................\.........\...\...\Entries
...................................\.........\...\...\Repository
...................................\.........\...\...\Root
...................................\.........\...\README.txt
...................................\.........\...\STATUS.txt
...................................\.........\...\usb_doc.pdf
...................................\.........\rtl
...................................\.........\...\CVS
...................................\.........\...\...\Entries
...................................\.........\...\...\Repository
...................................\.........\...\...\Root
...................................\.........\...\verilog
...................................\.........\...\.......\CVS
...................................\.........\...\.......\...\Entries
...................................\.........\...\.......\...\Repository
...................................\.........\...\.......\...\Root
...................................\.........\...\.......\usbf_crc16.v
...................................\.........\...\.......\usbf_crc5.v
...................................\.........\...\.......\usbf_defines.v
...................................\.........\...\.......\usbf_ep_rf.v
...................................\.........\...\.......\usbf_ep_rf_dummy.v
...................................\.........\...\.......\usbf_idma.v
...................................\.........\...\.......\usbf_mem_arb.v
...................................\.........\...\.......\usbf_pa.v
...................................\.........\...\.......\usbf_pd.v
...................................\.........\...\.......\usbf_pe.v
...................................\.........\...\.......\usbf_pl.v
...................................\.........\...\.......\usbf_rf.v
...................................\.........\...\.......\usbf_top.v
...................................\.........\...\.......\usbf_utmi_if.v
...................................\.........\...\.......\usbf_utmi_ls.v
...................................\.........\...\.......\usbf_wb.v
...................................\.........\sim
...................................\.........\...\CVS
...................................\.........\...\...\Entries
...................................\.........\...\...\Repository
...................................\.........\...\...\Root
...................................\.........\...\rtl_sim
...................................\.........\...\.......\bin
...................................\.........\...\.......\...\CVS
...................................\.........\...\.......\...\...\Entries
...................................\.........\...\.......\...\...\Repository
...................................\.........\...\.......\...\...\Root
...................................\.........\...\.......\CVS
...................................\.........\...\.......\...\Entries
...................................\.........\...\.......\...\Repository
...................................\.........\...\.......\...\Root
...................................\.........\...\.......\run
...................................\.........\...\.......\...\CVS
...................................\.........\...\....