文件名称:aes128
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AES实现的效率如面积、吞吐量和功耗等，主要是由列混合变换和S 盒的实现决定的。S 盒单元的实现成为设
计的重点，它的硬件实现在很大程度上决定着整个芯片的面积大小。
-AES to achieve efficiency, such as area, throughput and power consumption, mainly by the S box column mixing transformation and the realization of decision. S box unit designed to achieve to become the focus of its hardware implementation to a large extent determine the size of the entire chip area.
计的重点，它的硬件实现在很大程度上决定着整个芯片的面积大小。
-AES to achieve efficiency, such as area, throughput and power consumption, mainly by the S box column mixing transformation and the realization of decision. S box unit designed to achieve to become the focus of its hardware implementation to a large extent determine the size of the entire chip area.
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下载文件列表
aes128\rtl\a.v
......\...\aes_cipher_top.v
......\...\aes_key_expand_128.v
......\...\aes_rcon.v
......\...\aes_sbox.v
......\...\timescale.v
......\aes_128\1.cr.mti
......\.......\1.mpf
......\.......\aes_128.fsdb
......\.......\aes_cipher_top.v
......\.......\aes_key_expand_128.v
......\.......\aes_rcon.v
......\.......\gf_sbox.v
......\.......\readme.txt
......\.......\test_bench_top.v
......\.......\timescale.v
......\.......\transcript
......\.......\work\_info
......\.......\....\test\verilog.asm
......\.......\....\....\_primary.dat
......\.......\....\....\_primary.vhd
......\.......\....\sbox_square\verilog.asm
......\.......\....\...........\_primary.dat
......\.......\....\...........\_primary.vhd
......\.......\....\.....multip_e\verilog.asm
......\.......\....\.............\_primary.dat
......\.......\....\.............\_primary.vhd
......\.......\....\...........\verilog.asm
......\.......\....\...........\_primary.dat
......\.......\....\...........\_primary.vhd
......\.......\....\.....inverse\verilog.asm
......\.......\....\............\_primary.dat
......\.......\....\............\_primary.vhd
......\.......\....\gf_sbox\verilog.asm
......\.......\....\.......\_primary.dat
......\.......\....\.......\_primary.vhd
......\.......\....\aes_sbox\verilog.asm
......\.......\....\........\_primary.dat
......\.......\....\........\_primary.vhd
......\.......\....\....rcon\verilog.asm
......\.......\....\........\_primary.dat
......\.......\....\........\_primary.vhd
......\.......\....\....key_expand_128\verilog.asm
......\.......\....\..................\_primary.dat
......\.......\....\..................\_primary.vhd
......\.......\....\....cipher_top\verilog.asm
......\.......\....\..............\_primary.dat
......\.......\....\..............\_primary.vhd
......\.......\....\test
......\.......\....\sbox_square
......\.......\....\sbox_multip_e
......\.......\....\sbox_multip
......\.......\....\sbox_inverse
......\.......\....\gf_sbox
......\.......\....\aes_sbox
......\.......\....\aes_rcon
......\.......\....\aes_key_expand_128
......\.......\....\aes_cipher_top
......\.......\work
......\rtl
......\aes_128
aes128
......\...\aes_cipher_top.v
......\...\aes_key_expand_128.v
......\...\aes_rcon.v
......\...\aes_sbox.v
......\...\timescale.v
......\aes_128\1.cr.mti
......\.......\1.mpf
......\.......\aes_128.fsdb
......\.......\aes_cipher_top.v
......\.......\aes_key_expand_128.v
......\.......\aes_rcon.v
......\.......\gf_sbox.v
......\.......\readme.txt
......\.......\test_bench_top.v
......\.......\timescale.v
......\.......\transcript
......\.......\work\_info
......\.......\....\test\verilog.asm
......\.......\....\....\_primary.dat
......\.......\....\....\_primary.vhd
......\.......\....\sbox_square\verilog.asm
......\.......\....\...........\_primary.dat
......\.......\....\...........\_primary.vhd
......\.......\....\.....multip_e\verilog.asm
......\.......\....\.............\_primary.dat
......\.......\....\.............\_primary.vhd
......\.......\....\...........\verilog.asm
......\.......\....\...........\_primary.dat
......\.......\....\...........\_primary.vhd
......\.......\....\.....inverse\verilog.asm
......\.......\....\............\_primary.dat
......\.......\....\............\_primary.vhd
......\.......\....\gf_sbox\verilog.asm
......\.......\....\.......\_primary.dat
......\.......\....\.......\_primary.vhd
......\.......\....\aes_sbox\verilog.asm
......\.......\....\........\_primary.dat
......\.......\....\........\_primary.vhd
......\.......\....\....rcon\verilog.asm
......\.......\....\........\_primary.dat
......\.......\....\........\_primary.vhd
......\.......\....\....key_expand_128\verilog.asm
......\.......\....\..................\_primary.dat
......\.......\....\..................\_primary.vhd
......\.......\....\....cipher_top\verilog.asm
......\.......\....\..............\_primary.dat
......\.......\....\..............\_primary.vhd
......\.......\....\test
......\.......\....\sbox_square
......\.......\....\sbox_multip_e
......\.......\....\sbox_multip
......\.......\....\sbox_inverse
......\.......\....\gf_sbox
......\.......\....\aes_sbox
......\.......\....\aes_rcon
......\.......\....\aes_key_expand_128
......\.......\....\aes_cipher_top
......\.......\work
......\rtl
......\aes_128
aes128