文件名称:74HC283
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74ls283 基于verilog语言的实现 源程序在压缩包的hdl文件夹中-74ls161 language based on the realization of verilog source package in compressed folder hdl
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下载文件列表
74hc283
.......\74hc238.prj
.......\component
.......\constraint
.......\coreconsole
.......\designer
.......\........\impl1
.......\........\.....\adder4.adb
.......\........\.....\adder4.dtf
.......\........\.....\..........\verify.log
.......\........\.....\adder4.ide_des
.......\........\.....\adder4.pdb
.......\........\.....\adder4.pdb.depends
.......\........\.....\adder4.tcl
.......\........\.....\adder4_fp
.......\........\.....\.........\$$FlashPro_07294.L$$
.......\........\.....\.........\adder4.log
.......\........\.....\.........\adder4.pro
.......\........\.....\.........\projectData
.......\........\.....\.........\...........\adder4.pdb
.......\........\.....\designer.log
.......\........\.....\simulation
.......\hdl
.......\...\74hc238.v
.......\phy_synthesis
.......\simulation
.......\..........\modelsim.ini
.......\..........\modelsim.log
.......\..........\presynth
.......\..........\........\adder4
.......\..........\........\......\verilog.psm
.......\..........\........\......\_primary.dat
.......\..........\........\......\_primary.dbs
.......\..........\........\......\_primary.vhd
.......\..........\........\testbench
.......\..........\........\.........\verilog.psm
.......\..........\........\.........\_primary.dat
.......\..........\........\.........\_primary.dbs
.......\..........\........\.........\_primary.vhd
.......\..........\........\_info
.......\..........\........\_temp
.......\..........\........\_vmake
.......\..........\run.do
.......\..........\vsim.wlf
.......\smartgen
.......\........\smartgen.aws
.......\stimulus
.......\........\testbench.v
.......\synthesis
.......\.........\adder4.areasrr
.......\.........\adder4.edn
.......\.........\adder4.fse
.......\.........\adder4.htm
.......\.........\adder4.map
.......\.........\adder4.pdc
.......\.........\adder4.sap
.......\.........\adder4.sdf
.......\.........\adder4.so
.......\.........\adder4.srd
.......\.........\adder4.srm
.......\.........\adder4.srr
.......\.........\adder4.srs
.......\.........\adder4.szr
.......\.........\adder4.tlg
.......\.........\adder4_sdc.sdc
.......\.........\adder4_syn.prj
.......\.........\backup
.......\.........\coreip
.......\.........\run_options.txt
.......\.........\stdout.log
.......\.........\syntmp
.......\.........\......\adder4.plg
.......\.........\......\adder4_flink.htm
.......\.........\......\adder4_srr.htm
.......\.........\......\adder4_toc.htm
.......\.........\......\sap.log
.......\viewdraw
.......\........\sch
.......\........\sym
.......\........\vf
.......\........\..\project.lst
.......\........\viewdraw.ini
.......\........\wir
74hc283.pdf
.......\74hc238.prj
.......\component
.......\constraint
.......\coreconsole
.......\designer
.......\........\impl1
.......\........\.....\adder4.adb
.......\........\.....\adder4.dtf
.......\........\.....\..........\verify.log
.......\........\.....\adder4.ide_des
.......\........\.....\adder4.pdb
.......\........\.....\adder4.pdb.depends
.......\........\.....\adder4.tcl
.......\........\.....\adder4_fp
.......\........\.....\.........\$$FlashPro_07294.L$$
.......\........\.....\.........\adder4.log
.......\........\.....\.........\adder4.pro
.......\........\.....\.........\projectData
.......\........\.....\.........\...........\adder4.pdb
.......\........\.....\designer.log
.......\........\.....\simulation
.......\hdl
.......\...\74hc238.v
.......\phy_synthesis
.......\simulation
.......\..........\modelsim.ini
.......\..........\modelsim.log
.......\..........\presynth
.......\..........\........\adder4
.......\..........\........\......\verilog.psm
.......\..........\........\......\_primary.dat
.......\..........\........\......\_primary.dbs
.......\..........\........\......\_primary.vhd
.......\..........\........\testbench
.......\..........\........\.........\verilog.psm
.......\..........\........\.........\_primary.dat
.......\..........\........\.........\_primary.dbs
.......\..........\........\.........\_primary.vhd
.......\..........\........\_info
.......\..........\........\_temp
.......\..........\........\_vmake
.......\..........\run.do
.......\..........\vsim.wlf
.......\smartgen
.......\........\smartgen.aws
.......\stimulus
.......\........\testbench.v
.......\synthesis
.......\.........\adder4.areasrr
.......\.........\adder4.edn
.......\.........\adder4.fse
.......\.........\adder4.htm
.......\.........\adder4.map
.......\.........\adder4.pdc
.......\.........\adder4.sap
.......\.........\adder4.sdf
.......\.........\adder4.so
.......\.........\adder4.srd
.......\.........\adder4.srm
.......\.........\adder4.srr
.......\.........\adder4.srs
.......\.........\adder4.szr
.......\.........\adder4.tlg
.......\.........\adder4_sdc.sdc
.......\.........\adder4_syn.prj
.......\.........\backup
.......\.........\coreip
.......\.........\run_options.txt
.......\.........\stdout.log
.......\.........\syntmp
.......\.........\......\adder4.plg
.......\.........\......\adder4_flink.htm
.......\.........\......\adder4_srr.htm
.......\.........\......\adder4_toc.htm
.......\.........\......\sap.log
.......\viewdraw
.......\........\sch
.......\........\sym
.......\........\vf
.......\........\..\project.lst
.......\........\viewdraw.ini
.......\........\wir
74hc283.pdf