文件名称:74hc138
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74ls138 基于verilog语言的实现 -Verilog language 74ls138 based on the realization of
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下载文件列表
74hc138
.......\74hc138.prj
.......\component
.......\constraint
.......\coreconsole
.......\designer
.......\........\impl1
.......\........\.....\decoder_38.adb
.......\........\.....\decoder_38.dtf
.......\........\.....\..............\verify.log
.......\........\.....\decoder_38.ide_des
.......\........\.....\decoder_38.pdb
.......\........\.....\decoder_38.pdb.depends
.......\........\.....\decoder_38.tcl
.......\........\.....\decoder_38_ba.sdf
.......\........\.....\decoder_38_ba.v
.......\........\.....\designer.log
.......\........\.....\simulation
.......\hdl
.......\...\74hc138.v
.......\phy_synthesis
.......\simulation
.......\..........\modelsim.ini
.......\..........\modelsim.ini.sav
.......\..........\modelsim.log
.......\..........\presynth
.......\..........\........\decoder_38
.......\..........\........\..........\verilog.psm
.......\..........\........\..........\_primary.dat
.......\..........\........\..........\_primary.dbs
.......\..........\........\..........\_primary.vhd
.......\..........\........\testbench
.......\..........\........\.........\verilog.psm
.......\..........\........\.........\_primary.dat
.......\..........\........\.........\_primary.dbs
.......\..........\........\.........\_primary.vhd
.......\..........\........\_info
.......\..........\........\_temp
.......\..........\........\.....\vlogzyq214
.......\..........\run.do
.......\..........\vsim.wlf
.......\smartgen
.......\........\smartgen.aws
.......\stimulus
.......\........\testbench.v
.......\synthesis
.......\.........\backup
.......\.........\......\decoder_38.srr
.......\.........\coreip
.......\.........\decoder_38.areasrr
.......\.........\decoder_38.edn
.......\.........\decoder_38.fse
.......\.........\decoder_38.htm
.......\.........\decoder_38.map
.......\.........\decoder_38.pdc
.......\.........\decoder_38.sap
.......\.........\decoder_38.sdf
.......\.........\decoder_38.so
.......\.........\decoder_38.srd
.......\.........\decoder_38.srm
.......\.........\decoder_38.srr
.......\.........\decoder_38.srs
.......\.........\decoder_38.szr
.......\.........\decoder_38.tlg
.......\.........\decoder_38_sdc.sdc
.......\.........\decoder_38_syn.prj
.......\.........\run_options.txt
.......\.........\stdout.log
.......\.........\syntmp
.......\.........\......\decoder_38.plg
.......\.........\......\decoder_38_flink.htm
.......\.........\......\decoder_38_srr.htm
.......\.........\......\decoder_38_toc.htm
.......\.........\......\sap.log
.......\viewdraw
.......\........\sch
.......\........\sym
.......\........\vf
.......\........\..\project.lst
.......\........\viewdraw.ini
.......\........\wir
74hc138.pdf
.......\74hc138.prj
.......\component
.......\constraint
.......\coreconsole
.......\designer
.......\........\impl1
.......\........\.....\decoder_38.adb
.......\........\.....\decoder_38.dtf
.......\........\.....\..............\verify.log
.......\........\.....\decoder_38.ide_des
.......\........\.....\decoder_38.pdb
.......\........\.....\decoder_38.pdb.depends
.......\........\.....\decoder_38.tcl
.......\........\.....\decoder_38_ba.sdf
.......\........\.....\decoder_38_ba.v
.......\........\.....\designer.log
.......\........\.....\simulation
.......\hdl
.......\...\74hc138.v
.......\phy_synthesis
.......\simulation
.......\..........\modelsim.ini
.......\..........\modelsim.ini.sav
.......\..........\modelsim.log
.......\..........\presynth
.......\..........\........\decoder_38
.......\..........\........\..........\verilog.psm
.......\..........\........\..........\_primary.dat
.......\..........\........\..........\_primary.dbs
.......\..........\........\..........\_primary.vhd
.......\..........\........\testbench
.......\..........\........\.........\verilog.psm
.......\..........\........\.........\_primary.dat
.......\..........\........\.........\_primary.dbs
.......\..........\........\.........\_primary.vhd
.......\..........\........\_info
.......\..........\........\_temp
.......\..........\........\.....\vlogzyq214
.......\..........\run.do
.......\..........\vsim.wlf
.......\smartgen
.......\........\smartgen.aws
.......\stimulus
.......\........\testbench.v
.......\synthesis
.......\.........\backup
.......\.........\......\decoder_38.srr
.......\.........\coreip
.......\.........\decoder_38.areasrr
.......\.........\decoder_38.edn
.......\.........\decoder_38.fse
.......\.........\decoder_38.htm
.......\.........\decoder_38.map
.......\.........\decoder_38.pdc
.......\.........\decoder_38.sap
.......\.........\decoder_38.sdf
.......\.........\decoder_38.so
.......\.........\decoder_38.srd
.......\.........\decoder_38.srm
.......\.........\decoder_38.srr
.......\.........\decoder_38.srs
.......\.........\decoder_38.szr
.......\.........\decoder_38.tlg
.......\.........\decoder_38_sdc.sdc
.......\.........\decoder_38_syn.prj
.......\.........\run_options.txt
.......\.........\stdout.log
.......\.........\syntmp
.......\.........\......\decoder_38.plg
.......\.........\......\decoder_38_flink.htm
.......\.........\......\decoder_38_srr.htm
.......\.........\......\decoder_38_toc.htm
.......\.........\......\sap.log
.......\viewdraw
.......\........\sch
.......\........\sym
.......\........\vf
.......\........\..\project.lst
.......\........\viewdraw.ini
.......\........\wir
74hc138.pdf