文件名称:fifo
- 所属分类：
- VHDL编程
- 资源属性：
- [ASM] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 40kb
- 下载次数：
- 0次
- 提 供 者：
- iechs******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
异步fifo，用Verilog编写，包含testbench，已经通过modelsim调试，内含文档和波形图-Asynchronous fifo, to prepare to use Verilog, including testbench, debug modelsim has passed, including documents and wave
相关搜索： fifo
VERILOG
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verilog
modelsim
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verilog
testbench
testbench
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FPGA
verilog
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adpcm
modelsim
FIFO
testbench
VERILOG
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FIFO
verilog
fifo
v
verilog
modelsim
testbench
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FIFO
FPGA
verilog
fifo
adpcm
modelsim
FIFO
testbench
(系统自动生成,下载前可以参看下载内容)
下载文件列表
0804214-段振华-fifo程序
.......................\fifo
.......................\....\fifo.cr.mti
.......................\....\fifo.mpf
.......................\....\fifo.v
.......................\....\fifo.v.bak
.......................\....\fifotb.v
.......................\....\fifotb.v.bak
.......................\....\transcript
.......................\....\vish_stacktrace.vstf
.......................\....\vsim.wlf
.......................\....\work
.......................\....\....\fifo
.......................\....\....\....\verilog.asm
.......................\....\....\....\_primary.dat
.......................\....\....\....\_primary.vhd
.......................\....\....\gray
.......................\....\....\....\verilog.asm
.......................\....\....\....\_primary.dat
.......................\....\....\....\_primary.vhd
.......................\....\....\testfifo
.......................\....\....\........\verilog.asm
.......................\....\....\........\_primary.dat
.......................\....\....\........\_primary.vhd
.......................\....\....\_info
.......................\fifo程序说明.doc
.......................\fifo
.......................\....\fifo.cr.mti
.......................\....\fifo.mpf
.......................\....\fifo.v
.......................\....\fifo.v.bak
.......................\....\fifotb.v
.......................\....\fifotb.v.bak
.......................\....\transcript
.......................\....\vish_stacktrace.vstf
.......................\....\vsim.wlf
.......................\....\work
.......................\....\....\fifo
.......................\....\....\....\verilog.asm
.......................\....\....\....\_primary.dat
.......................\....\....\....\_primary.vhd
.......................\....\....\gray
.......................\....\....\....\verilog.asm
.......................\....\....\....\_primary.dat
.......................\....\....\....\_primary.vhd
.......................\....\....\testfifo
.......................\....\....\........\verilog.asm
.......................\....\....\........\_primary.dat
.......................\....\....\........\_primary.vhd
.......................\....\....\_info
.......................\fifo程序说明.doc