文件名称:XiaYuWen_8_RISC_CPU
介绍说明－－下载内容均来自于网络，请自行研究使用
夏宇闻8位RISC_CPU的完整代码+TESTBENCH（已调试）
modelsim工程文件，包括书中所测试的三个程序和相关数据，绝对可用~所有信号名均遵从原书。在论坛中没有找到testbench的，只有一个mcu的代码，但很多和书中的是不一样的，自己改了下下~`````大家多多支持啊~`我觉得书中也还是有些不尽如人意的地方，如clk_gen.v中clk2,clk4是没有用的，assign clk1=~clk再用clk1的negedge clk1来触发各个module也是不太好的，会使时序恶化，综合时很可能会setup vio的，所以觉得直接用clk的上升沿来触发各个module比较好-XIA Yu-Wen 8 RISC_CPU complete code+ TESTBENCH (has debug) modelsim project documents, including the book by the three test procedures and related data, the absolute available ~ all signals were found in compliance with the original name. Not found in the forums Testbench, and there is only one mcu code, but many and the book is not the same as he changed a lot of support under the U.S. ~````` ah ~ `I think the book is still some uncertainty unsatisfactory places, such as clk_gen.v in clk2, clk4 is of no use, assign clk1 = ~ clk reuse CLK1 of negedge clk1 to trigger module is not all good, cause the deterioration of timing, synthesis is likely to setup vio, therefore, feel that the direct use of the rising edge of clk to trigger each module is better
modelsim工程文件，包括书中所测试的三个程序和相关数据，绝对可用~所有信号名均遵从原书。在论坛中没有找到testbench的，只有一个mcu的代码，但很多和书中的是不一样的，自己改了下下~`````大家多多支持啊~`我觉得书中也还是有些不尽如人意的地方，如clk_gen.v中clk2,clk4是没有用的，assign clk1=~clk再用clk1的negedge clk1来触发各个module也是不太好的，会使时序恶化，综合时很可能会setup vio的，所以觉得直接用clk的上升沿来触发各个module比较好-XIA Yu-Wen 8 RISC_CPU complete code+ TESTBENCH (has debug) modelsim project documents, including the book by the three test procedures and related data, the absolute available ~ all signals were found in compliance with the original name. Not found in the forums Testbench, and there is only one mcu code, but many and the book is not the same as he changed a lot of support under the U.S. ~````` ah ~ `I think the book is still some uncertainty unsatisfactory places, such as clk_gen.v in clk2, clk4 is of no use, assign clk1 = ~ clk reuse CLK1 of negedge clk1 to trigger module is not all good, cause the deterioration of timing, synthesis is likely to setup vio, therefore, feel that the direct use of the rising edge of clk to trigger each module is better
(系统自动生成,下载前可以参看下载内容)
下载文件列表
RISC_CPU
........\accum.v
........\accum.v.bak
........\addr_decode.v
........\addr_decode.v.bak
........\adr.v
........\adr.v.bak
........\alu.v
........\clk_gen.v
........\clk_gen.v.bak
........\counter.v
........\counter.v.bak
........\cpu.v
........\cpu.v.bak
........\cputop.v
........\cputop.v.bak
........\datactl.v
........\datactl.v.bak
........\machine.v
........\machine.v.bak
........\machinectl.v
........\machinectl.v.bak
........\ram.v
........\ram.v.bak
........\register.v
........\register.v.bak
........\RISC_CPU.cr.mti
........\RISC_CPU.mpf
........\rom.v
........\rom.v.bak
........\test1_dat.txt
........\test1_pro.txt
........\test2_dat.txt
........\test2_pro.txt
........\test3_dat.txt
........\test3_pro.txt
........\vsim.wlf
........\work
........\....\accum
........\....\.....\verilog.asm
........\....\.....\_primary.dat
........\....\.....\_primary.dbs
........\....\.....\_primary.vhd
........\....\addr_decode
........\....\...........\verilog.asm
........\....\...........\_primary.dat
........\....\...........\_primary.dbs
........\....\...........\_primary.vhd
........\....\adr
........\....\...\verilog.asm
........\....\...\_primary.dat
........\....\...\_primary.dbs
........\....\...\_primary.vhd
........\....\alu
........\....\...\verilog.asm
........\....\...\_primary.dat
........\....\...\_primary.dbs
........\....\...\_primary.vhd
........\....\clk_gen
........\....\.......\verilog.asm
........\....\.......\_primary.dat
........\....\.......\_primary.dbs
........\....\.......\_primary.vhd
........\....\counter
........\....\.......\verilog.asm
........\....\.......\_primary.dat
........\....\.......\_primary.dbs
........\....\.......\_primary.vhd
........\....\cpu
........\....\...\verilog.asm
........\....\...\_primary.dat
........\....\...\_primary.dbs
........\....\...\_primary.vhd
........\....\cputop
........\....\......\verilog.asm
........\....\......\_primary.dat
........\....\......\_primary.dbs
........\....\......\_primary.vhd
........\....\datactl
........\....\.......\verilog.asm
........\....\.......\_primary.dat
........\....\.......\_primary.dbs
........\....\.......\_primary.vhd
........\....\machine
........\....\.......\verilog.asm
........\....\.......\_primary.dat
........\....\.......\_primary.dbs
........\....\.......\_primary.vhd
........\....\machinectl
........\....\..........\verilog.asm
........\....\..........\_primary.dat
........\....\..........\_primary.dbs
........\....\..........\_primary.vhd
........\....\ram
........\....\...\verilog.asm
........\....\...\_primary.dat
........\....\...\_primary.dbs
........\....\...\_primary.vhd
........\....\register
........\....\........\verilog.asm
........\accum.v
........\accum.v.bak
........\addr_decode.v
........\addr_decode.v.bak
........\adr.v
........\adr.v.bak
........\alu.v
........\clk_gen.v
........\clk_gen.v.bak
........\counter.v
........\counter.v.bak
........\cpu.v
........\cpu.v.bak
........\cputop.v
........\cputop.v.bak
........\datactl.v
........\datactl.v.bak
........\machine.v
........\machine.v.bak
........\machinectl.v
........\machinectl.v.bak
........\ram.v
........\ram.v.bak
........\register.v
........\register.v.bak
........\RISC_CPU.cr.mti
........\RISC_CPU.mpf
........\rom.v
........\rom.v.bak
........\test1_dat.txt
........\test1_pro.txt
........\test2_dat.txt
........\test2_pro.txt
........\test3_dat.txt
........\test3_pro.txt
........\vsim.wlf
........\work
........\....\accum
........\....\.....\verilog.asm
........\....\.....\_primary.dat
........\....\.....\_primary.dbs
........\....\.....\_primary.vhd
........\....\addr_decode
........\....\...........\verilog.asm
........\....\...........\_primary.dat
........\....\...........\_primary.dbs
........\....\...........\_primary.vhd
........\....\adr
........\....\...\verilog.asm
........\....\...\_primary.dat
........\....\...\_primary.dbs
........\....\...\_primary.vhd
........\....\alu
........\....\...\verilog.asm
........\....\...\_primary.dat
........\....\...\_primary.dbs
........\....\...\_primary.vhd
........\....\clk_gen
........\....\.......\verilog.asm
........\....\.......\_primary.dat
........\....\.......\_primary.dbs
........\....\.......\_primary.vhd
........\....\counter
........\....\.......\verilog.asm
........\....\.......\_primary.dat
........\....\.......\_primary.dbs
........\....\.......\_primary.vhd
........\....\cpu
........\....\...\verilog.asm
........\....\...\_primary.dat
........\....\...\_primary.dbs
........\....\...\_primary.vhd
........\....\cputop
........\....\......\verilog.asm
........\....\......\_primary.dat
........\....\......\_primary.dbs
........\....\......\_primary.vhd
........\....\datactl
........\....\.......\verilog.asm
........\....\.......\_primary.dat
........\....\.......\_primary.dbs
........\....\.......\_primary.vhd
........\....\machine
........\....\.......\verilog.asm
........\....\.......\_primary.dat
........\....\.......\_primary.dbs
........\....\.......\_primary.vhd
........\....\machinectl
........\....\..........\verilog.asm
........\....\..........\_primary.dat
........\....\..........\_primary.dbs
........\....\..........\_primary.vhd
........\....\ram
........\....\...\verilog.asm
........\....\...\_primary.dat
........\....\...\_primary.dbs
........\....\...\_primary.vhd
........\....\register
........\....\........\verilog.asm