文件名称:arbiter
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一个用verilog编写的总线仲裁程序。多个设备共享总线,不同设备的优先级是变化的,保证每个设备都有公平的使用总线的机会。-Verilog prepared a bus with arbitration proceedings. Multiple devices share the bus, the priority of different devices is changing to ensure that each device will have a fair opportunity to use the bus.
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arbiter
.......\arb.v
.......\arb_fsm.v
.......\arb_tb.v
.......\counter.v
.......\monitor.v
.......\transcript
.......\xact.v
.......\arb.v
.......\arb_fsm.v
.......\arb_tb.v
.......\counter.v
.......\monitor.v
.......\transcript
.......\xact.v