文件名称:VLSIrtl_spi
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verilog语言写的SPI接口,全同步设计,低门数,可以很容易应用到嵌入设计方案中.-Verilog language to write the SPI interface, all synchronous design, low gate count. it is very easy to use embedded design programs.
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下载文件列表
rtl_spi
.......\spi.v
.......\spi_bitcounter.v
.......\spi_bitcounter_rtl.v
.......\spi_bytecounter.v
.......\spi_bytecounter_rtl.v
.......\spi_clkdiv_count.v
.......\spi_clkdiv_count_rtl.v
.......\spi_clock_gen.v
.......\spi_comp3_ge.v
.......\spi_comp3_ge_rtl.v
.......\spi_comp3_se.v
.......\spi_comp3_se_rtl.v
.......\spi_control.v
.......\spi_core.v
.......\spi_cs_cnt.v
.......\spi_cs_cnt_rtl.v
.......\spi_equal3.v
.......\spi_equal3_rtl.v
.......\spi_fifo.v
.......\spi_it.v
.......\spi_map.v
.......\spi_page_cnt.v
.......\spi_page_cnt_rtl.v
.......\spi_regs.v
.......\spi_tx_rx.v
.......\spi_waitcounter.v
.......\spi_waitcounter_rtl.v
.......\spi.v
.......\spi_bitcounter.v
.......\spi_bitcounter_rtl.v
.......\spi_bytecounter.v
.......\spi_bytecounter_rtl.v
.......\spi_clkdiv_count.v
.......\spi_clkdiv_count_rtl.v
.......\spi_clock_gen.v
.......\spi_comp3_ge.v
.......\spi_comp3_ge_rtl.v
.......\spi_comp3_se.v
.......\spi_comp3_se_rtl.v
.......\spi_control.v
.......\spi_core.v
.......\spi_cs_cnt.v
.......\spi_cs_cnt_rtl.v
.......\spi_equal3.v
.......\spi_equal3_rtl.v
.......\spi_fifo.v
.......\spi_it.v
.......\spi_map.v
.......\spi_page_cnt.v
.......\spi_page_cnt_rtl.v
.......\spi_regs.v
.......\spi_tx_rx.v
.......\spi_waitcounter.v
.......\spi_waitcounter_rtl.v