文件名称:EP1C3_12_10_PHAS
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基于FPGA的移相式DDS正弦信号发生器的VHDL源代码，压缩包里是在Quartus里做的工程，FPGA用的是Cyclone1C3系列-FPGA-based phase-shifting of the DDS signal generator sine VHDL source code, compressed in the bag is done in Quartus Engineering, FPGA is used Cyclone1C3 Series
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下载文件列表
EP1C3_12_10_PHAS
................\ADDER10B.VHD
................\ADDER32B.VHD
................\cmp_state.ini
................\DATA
................\....\LUT10X10.HEX
................\....\LUT10X10.MIF
................\dds_vhdl.asm.rpt
................\DDS_VHDL.CDF
................\dds_vhdl.done
................\dds_vhdl.fit.summary
................\dds_vhdl.flow.rpt
................\dds_vhdl.map.summary
................\DDS_VHDL.PIN
................\DDS_VHDL.QPF
................\DDS_VHDL.QSF
................\DDS_VHDL.QWS
................\DDS_VHDL.SOF
................\dds_vhdl.tan.summary
................\DDS_VHDL.VHD
................\dds_vhdl_assignment_defaults.qdf
................\PLL20.VHD
................\README
................\......\GW48使用readme.txt
................\REG10B.VHD
................\REG32B.VHD
................\SIN_ROM.VHD
................\STP1.STP
................\ADDER10B.VHD
................\ADDER32B.VHD
................\cmp_state.ini
................\DATA
................\....\LUT10X10.HEX
................\....\LUT10X10.MIF
................\dds_vhdl.asm.rpt
................\DDS_VHDL.CDF
................\dds_vhdl.done
................\dds_vhdl.fit.summary
................\dds_vhdl.flow.rpt
................\dds_vhdl.map.summary
................\DDS_VHDL.PIN
................\DDS_VHDL.QPF
................\DDS_VHDL.QSF
................\DDS_VHDL.QWS
................\DDS_VHDL.SOF
................\dds_vhdl.tan.summary
................\DDS_VHDL.VHD
................\dds_vhdl_assignment_defaults.qdf
................\PLL20.VHD
................\README
................\......\GW48使用readme.txt
................\REG10B.VHD
................\REG32B.VHD
................\SIN_ROM.VHD
................\STP1.STP