文件名称:decoder

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 64kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • PUDN*****
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

一个verilog源代码,用于译码器的编程。-A verilog source code, for programming decoder.
相关搜索: decoder
verilog
decod

(系统自动生成,下载前可以参看下载内容)

下载文件列表

decoder

.......\ISE

.......\...\decoder

.......\...\.......\.untf

.......\...\.......\automake.log

.......\...\.......\bitgen.ut

.......\...\.......\decoder.bgn

.......\...\.......\decoder.bit

.......\...\.......\decoder.bld

.......\...\.......\decoder.cmd_log

.......\...\.......\decoder.dhp

.......\...\.......\decoder.drc

.......\...\.......\decoder.lfp

.......\...\.......\decoder.lso

.......\...\.......\decoder.mrp

.......\...\.......\decoder.nc1

.......\...\.......\decoder.ncd

.......\...\.......\decoder.ngc

.......\...\.......\decoder.ngd

.......\...\.......\decoder.ngm

.......\...\.......\decoder.ngr

.......\...\.......\decoder.npl

.......\...\.......\decoder.pad

.......\...\.......\decoder.pad_txt

.......\...\.......\decoder.par

.......\...\.......\decoder.pcf

.......\...\.......\decoder.placed_ncd_tracker

.......\...\.......\decoder.prj

.......\...\.......\decoder.routed_ncd_tracker

.......\...\.......\decoder.stx

.......\...\.......\decoder.syr

.......\...\.......\decoder.twr

.......\...\.......\decoder.twx

.......\...\.......\decoder.ucf

.......\...\.......\decoder.ucf.untf

.......\...\.......\decoder.ut

.......\...\.......\decoder.v

.......\...\.......\decoder.xpi

.......\...\.......\decoder_map.ncd

.......\...\.......\decoder_map.ngm

.......\...\.......\decoder_pad.csv

.......\...\.......\decoder_pad.txt

.......\...\.......\decoder_vhdl.prj

.......\...\.......\xst

.......\...\.......\...\work

.......\...\.......\...\....\hdllib.ref

.......\...\.......\...\....\vlg02

.......\...\.......\...\....\.....\decoder.bin

.......\...\.......\_ngo

.......\...\.......\....\netlist.lst

.......\...\.......\_pace.ucf

.......\...\.......\__projnav

.......\...\.......\.........\bitgen.rsp

.......\...\.......\.........\decoder.gfl

.......\...\.......\.........\decoder.xst

.......\...\.......\.........\decoder_flowplus.gfl

.......\...\.......\.........\decoder_ncdTOut_tcl.rsp

.......\...\.......\.........\ednTOngd_tcl.rsp

.......\...\.......\.........\map.log

.......\...\.......\.........\nc1TOncd_tcl.rsp

.......\...\.......\.........\par.log

.......\...\.......\.........\parentAssignPackagePinsApp_tcl.rsp

.......\...\.......\.........\posttrc.log

.......\...\.......\.........\runXst_tcl.rsp

.......\...\.......\__projnav.log

.......\modelsim

.......\........\decoder.cr.mti

.......\........\decoder.mpf

.......\........\vsim.wlf

.......\........\work

.......\........\....\decoder

.......\........\....\.......\verilog.asm

.......\........\....\.......\_primary.dat

.......\........\....\.......\_primary.vhd

.......\........\....\tb_decoder

.......\........\....\..........\verilog.asm

.......\........\....\..........\_primary.dat

.......\........\....\..........\_primary.vhd

.......\........\....\_info

.......\rtl

.......\...\decoder.v

.......\...\tb_decoder.v

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