文件名称:Example-b3-1
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ALTER FPGA/GPLD设计（初级篇）的源码，只是其中的一部分供大家参考，如果还有用到其他的，请联系我-ALTER FPGA/GPLD design (primary chapter) of the source, is only one part of it for public consultation, if there are other uses, please contact me
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下载文件列表
Example-b3-1
............\uart_regs
............\.........\core
............\.........\....\db
............\.........\....\myfifo_10.v
............\.........\....\myfifo_10_bb.v
............\.........\....\myfifo_10_waveforms.html
............\.........\....\myfifo_8.v
............\.........\....\myfifo_8_bb.v
............\.........\....\myfifo_8_waveforms.html
............\.........\dev
............\.........\...\chip_editor.acv
............\.........\...\cmp_state.ini
............\.........\...\db
............\.........\...\..\add_sub_1jh.tdf
............\.........\...\..\add_sub_1sh.tdf
............\.........\...\..\add_sub_2sh.tdf
............\.........\...\..\add_sub_3sh.tdf
............\.........\...\..\add_sub_6sh.tdf
............\.........\...\..\add_sub_dhh.tdf
............\.........\...\..\add_sub_ehh.tdf
............\.........\...\..\add_sub_fhh.tdf
............\.........\...\..\add_sub_fth.tdf
............\.........\...\..\add_sub_ihh.tdf
............\.........\...\..\add_sub_lth.tdf
............\.........\...\..\add_sub_rih.tdf
............\.........\...\..\altsyncram_4pl1.tdf
............\.........\...\..\altsyncram_apb1.tdf
............\.........\...\..\altsyncram_gml1.tdf
............\.........\...\..\altsyncram_mmb1.tdf
............\.........\...\..\a_dpfifo_4nl.tdf
............\.........\...\..\a_dpfifo_ac51.tdf
............\.........\...\..\a_dpfifo_jd51.tdf
............\.........\...\..\a_dpfifo_rll.tdf
............\.........\...\..\a_fefifo_66f.tdf
............\.........\...\..\a_fefifo_qve.tdf
............\.........\...\..\cntr_9d7.tdf
............\.........\...\..\cntr_re8.tdf
............\.........\...\..\dpram_81k.tdf
............\.........\...\..\dpram_ea21.tdf
............\.........\...\..\dpram_h2k.tdf
............\.........\...\..\dpram_nb21.tdf
............\.........\...\..\scfifo_3651.tdf
............\.........\...\..\scfifo_c751.tdf
............\.........\...\..\scfifo_eaq.tdf
............\.........\...\..\scfifo_nbq.tdf
............\.........\...\..\uart_regs-sim.vwf
............\.........\...\..\uart_regs.analyze_file.qmsg
............\.........\...\..\uart_regs.asm.qmsg
............\.........\...\..\uart_regs.cbx.xml
............\.........\...\..\uart_regs.cmp.kpt
............\.........\...\..\uart_regs.cmp.rdb
............\.........\...\..\uart_regs.dbp
............\.........\...\..\uart_regs.db_info
............\.........\...\..\uart_regs.eco.cdb
............\.........\...\..\uart_regs.eds_overflow
............\.........\...\..\uart_regs.fit.qmsg
............\.........\...\..\uart_regs.fnsim.cdb
............\.........\...\..\uart_regs.fnsim.hdb
............\.........\...\..\uart_regs.fnsim.qmsg
............\.........\...\..\uart_regs.hier_info
............\.........\...\..\uart_regs.hif
............\.........\...\..\uart_regs.map.hdb
............\.........\...\..\uart_regs.map.qmsg
............\.........\...\..\uart_regs.pre_map.cdb
............\.........\...\..\uart_regs.pre_map.hdb
............\.........\...\..\uart_regs.psp
............\.........\...\..\uart_regs.rtlv.hdb
............\.........\...\..\uart_regs.rtlv_sg.cdb
............\.........\...\..\uart_regs.rtlv_sg_swap.cdb
............\.........\...\..\uart_regs.sgdiff.cdb
............\.........\...\..\uart_regs.sgdiff.hdb
............\.........\...\..\uart_regs.sim.hdb
............\.........\...\..\uart_regs.sim.qmsg
............\.........\...\..\uart_regs.sim.rdb
............\.........\...\..\uart_regs.sim.vwf
............\.........\...\..\uart_regs.sld_design_entry.sci
............\.........\...\..\uart_regs.sld_design_entry_dsc.sci
............\.........\...\..\uart_regs.syn_hier_info
............\.........\...\..\uart_regs.tan.qmsg
............\.........\...\..\uart_regs_cmp.qrpt
............\.........\...\..\uart_regs_hier_info
............\.........\...\..\uart_regs_sim.qrpt
............\.........\...\..\uart_regs_syn_hier_info
............\.........\...\..\wed.zsf
............\.........\...\sim.cfg
............\.........\...\uart_regs.asm.rpt
............\.........\...\uart_regs.done
............\.........\...\uart_
............\uart_regs
............\.........\core
............\.........\....\db
............\.........\....\myfifo_10.v
............\.........\....\myfifo_10_bb.v
............\.........\....\myfifo_10_waveforms.html
............\.........\....\myfifo_8.v
............\.........\....\myfifo_8_bb.v
............\.........\....\myfifo_8_waveforms.html
............\.........\dev
............\.........\...\chip_editor.acv
............\.........\...\cmp_state.ini
............\.........\...\db
............\.........\...\..\add_sub_1jh.tdf
............\.........\...\..\add_sub_1sh.tdf
............\.........\...\..\add_sub_2sh.tdf
............\.........\...\..\add_sub_3sh.tdf
............\.........\...\..\add_sub_6sh.tdf
............\.........\...\..\add_sub_dhh.tdf
............\.........\...\..\add_sub_ehh.tdf
............\.........\...\..\add_sub_fhh.tdf
............\.........\...\..\add_sub_fth.tdf
............\.........\...\..\add_sub_ihh.tdf
............\.........\...\..\add_sub_lth.tdf
............\.........\...\..\add_sub_rih.tdf
............\.........\...\..\altsyncram_4pl1.tdf
............\.........\...\..\altsyncram_apb1.tdf
............\.........\...\..\altsyncram_gml1.tdf
............\.........\...\..\altsyncram_mmb1.tdf
............\.........\...\..\a_dpfifo_4nl.tdf
............\.........\...\..\a_dpfifo_ac51.tdf
............\.........\...\..\a_dpfifo_jd51.tdf
............\.........\...\..\a_dpfifo_rll.tdf
............\.........\...\..\a_fefifo_66f.tdf
............\.........\...\..\a_fefifo_qve.tdf
............\.........\...\..\cntr_9d7.tdf
............\.........\...\..\cntr_re8.tdf
............\.........\...\..\dpram_81k.tdf
............\.........\...\..\dpram_ea21.tdf
............\.........\...\..\dpram_h2k.tdf
............\.........\...\..\dpram_nb21.tdf
............\.........\...\..\scfifo_3651.tdf
............\.........\...\..\scfifo_c751.tdf
............\.........\...\..\scfifo_eaq.tdf
............\.........\...\..\scfifo_nbq.tdf
............\.........\...\..\uart_regs-sim.vwf
............\.........\...\..\uart_regs.analyze_file.qmsg
............\.........\...\..\uart_regs.asm.qmsg
............\.........\...\..\uart_regs.cbx.xml
............\.........\...\..\uart_regs.cmp.kpt
............\.........\...\..\uart_regs.cmp.rdb
............\.........\...\..\uart_regs.dbp
............\.........\...\..\uart_regs.db_info
............\.........\...\..\uart_regs.eco.cdb
............\.........\...\..\uart_regs.eds_overflow
............\.........\...\..\uart_regs.fit.qmsg
............\.........\...\..\uart_regs.fnsim.cdb
............\.........\...\..\uart_regs.fnsim.hdb
............\.........\...\..\uart_regs.fnsim.qmsg
............\.........\...\..\uart_regs.hier_info
............\.........\...\..\uart_regs.hif
............\.........\...\..\uart_regs.map.hdb
............\.........\...\..\uart_regs.map.qmsg
............\.........\...\..\uart_regs.pre_map.cdb
............\.........\...\..\uart_regs.pre_map.hdb
............\.........\...\..\uart_regs.psp
............\.........\...\..\uart_regs.rtlv.hdb
............\.........\...\..\uart_regs.rtlv_sg.cdb
............\.........\...\..\uart_regs.rtlv_sg_swap.cdb
............\.........\...\..\uart_regs.sgdiff.cdb
............\.........\...\..\uart_regs.sgdiff.hdb
............\.........\...\..\uart_regs.sim.hdb
............\.........\...\..\uart_regs.sim.qmsg
............\.........\...\..\uart_regs.sim.rdb
............\.........\...\..\uart_regs.sim.vwf
............\.........\...\..\uart_regs.sld_design_entry.sci
............\.........\...\..\uart_regs.sld_design_entry_dsc.sci
............\.........\...\..\uart_regs.syn_hier_info
............\.........\...\..\uart_regs.tan.qmsg
............\.........\...\..\uart_regs_cmp.qrpt
............\.........\...\..\uart_regs_hier_info
............\.........\...\..\uart_regs_sim.qrpt
............\.........\...\..\uart_regs_syn_hier_info
............\.........\...\..\wed.zsf
............\.........\...\sim.cfg
............\.........\...\uart_regs.asm.rpt
............\.........\...\uart_regs.done
............\.........\...\uart_