运行在FPGA上的Verilog程序(实现对ADC的控制)

..........................................\sample

..........................................\......\ADCINT.VHD

..........................................\......\db

..........................................\......\..\altsyncram_5hb2.tdf

..........................................\......\..\cmpr_5mh.tdf

..........................................\......\..\cntr_09b.tdf

..........................................\......\..\cntr_afd.tdf

..........................................\......\..\cntr_kkb.tdf

..........................................\......\..\cntr_lbc.tdf

..........................................\......\..\cntr_ria.tdf

..........................................\......\..\decode_9ie.tdf

..........................................\......\..\sample.asm.qmsg

..........................................\......\..\sample.cbx.xml

..........................................\......\..\sample.cmp.cdb

..........................................\......\..\sample.cmp.hdb

..........................................\......\..\sample.cmp.qrpt

..........................................\......\..\sample.cmp.rdb

..........................................\......\..\sample.cmp.tdb

..........................................\......\..\sample.cmp0.ddb

..........................................\......\..\sample.dbp

..........................................\......\..\sample.db_info

..........................................\......\..\sample.eco.cdb

..........................................\......\..\sample.eds_overflow

..........................................\......\..\sample.fit.qmsg

..........................................\......\..\sample.hier_info

..........................................\......\..\sample.hif

..........................................\......\..\sample.map.cdb

..........................................\......\..\sample.map.hdb

..........................................\......\..\sample.map.qmsg

..........................................\......\..\sample.pre_map.cdb

..........................................\......\..\sample.pre_map.hdb

..........................................\......\..\sample.psp

..........................................\......\..\sample.rpp.qmsg

..........................................\......\..\sample.rtlv.hdb

..........................................\......\..\sample.rtlv_sg.cdb

..........................................\......\..\sample.rtlv_sg_swap.cdb

..........................................\......\..\sample.sgate.rvd

..........................................\......\..\sample.sgate_sm.rvd

..........................................\......\..\sample.sgdiff.cdb

..........................................\......\..\sample.sgdiff.hdb

..........................................\......\..\sample.signalprobe.cdb

..........................................\......\..\sample.sim.hdb

..........................................\......\..\sample.sim.qmsg

..........................................\......\..\sample.sim.qrpt

..........................................\......\..\sample.sim.rdb

..........................................\......\..\sample.sim.vwf

..........................................\......\..\sample.sld_design_entry.sci

..........................................\......\..\sample.sld_design_entry_dsc.sci

..........................................\......\..\sample.smp_dump.txt

..........................................\......\..\sample.syn_hier_info

..........................................\......\..\sample.tan.qmsg

..........................................\......\sample.asm.rpt

..........................................\......\sample.bsf

..........................................\......\sample.cdf

..........................................\......\sample.done

..........................................\......\sample.fit.eqn

..........................................\......\sample.fit.rpt

..........................................\......\sample.fit.summary

..........................................\......\sample.flow.rpt

..............................