文件名称:I2C_HDL
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I2C bus HDL source and testbench
相关搜索： i2c
testbench
testbench
i2c
master
verilog
testben
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testbench
ilo
pudn
i2c
I2C
Veril
spi
verilog
and
testbench
I2C
Verilo
FPGA
verilog
i2c
I2C
testbench
testbench
i2c
master
verilog
testben
i2c
testbench
ilo
pudn
i2c
I2C
Veril
spi
verilog
and
testbench
I2C
Verilo
FPGA
verilog
i2c
I2C
(系统自动生成,下载前可以参看下载内容)
下载文件列表
I2C总线VHDL Verilog HDL源码
...........................\bench
...........................\.....\CVS
...........................\.....\...\Entries
...........................\.....\...\Repository
...........................\.....\...\Root
...........................\.....\verilog
...........................\.....\.......\CVS
...........................\.....\.......\...\Entries
...........................\.....\.......\...\Repository
...........................\.....\.......\...\Root
...........................\.....\.......\i2c_slave_model.v
...........................\.....\.......\spi_slave_model.v
...........................\.....\.......\tst_bench_top.v
...........................\.....\.......\wb_master_model.v
...........................\doc
...........................\...\CVS
...........................\...\...\Entries
...........................\...\...\Repository
...........................\...\...\Root
...........................\...\i2c_specs.pdf
...........................\...\src
...........................\...\...\CVS
...........................\...\...\...\Entries
...........................\...\...\...\Repository
...........................\...\...\...\Root
...........................\...\...\I2C_specs.doc
...........................\rtl
...........................\...\CVS
...........................\...\...\Entries
...........................\...\...\Repository
...........................\...\...\Root
...........................\...\verilog
...........................\...\.......\CVS
...........................\...\.......\...\Entries
...........................\...\.......\...\Repository
...........................\...\.......\...\Root
...........................\...\.......\i2c_master_bit_ctrl.v
...........................\...\.......\i2c_master_byte_ctrl.v
...........................\...\.......\i2c_master_defines.v
...........................\...\.......\i2c_master_top.v
...........................\...\.......\timescale.v
...........................\...\vhdl
...........................\...\....\CVS
...........................\...\....\...\Entries
...........................\...\....\...\Repository
...........................\...\....\...\Root
...........................\...\....\I2C.VHD
...........................\...\....\i2c_master_bit_ctrl.vhd
...........................\...\....\i2c_master_byte_ctrl.vhd
...........................\...\....\i2c_master_top.vhd
...........................\...\....\readme
...........................\...\....\tst_ds1621.vhd
...........................\sim
...........................\...\CVS
...........................\...\...\Entries
...........................\...\...\Repository
...........................\...\...\Root
...........................\...\i2c_verilog
...........................\...\...........\CVS
...........................\...\...........\...\Entries
...........................\...\...........\...\Repository
...........................\...\...........\...\Root
...........................\...\...........\run
...........................\...\...........\...\bench.vcd
...........................\...\...........\...\CVS
...........................\...\...........\...\...\Entries
...........................\...\...........\...\...\Repository
...........................\...\...........\...\...\Root
...........................\...\...........\...\INCA_libs
...........................\...\...........\...\.........\CVS
...........................\...\...........\...\.........\...\Entries
...........................\...\...........\...\.........\...\Repository
...........................\...\...........\...\.........\...\Root
...........................\...\...........\...\ncverilog.key
...........................\...\...........\...\ncverilog.log
...........................\...\...........\...\run
...........................\...\...........\...\waves
...........................\...\...........\...\.....\CVS
...........................\...\...........\...\.....\...\Entries
...........................\...\...........\...\.....\...\Repository
.......................
...........................\bench
...........................\.....\CVS
...........................\.....\...\Entries
...........................\.....\...\Repository
...........................\.....\...\Root
...........................\.....\verilog
...........................\.....\.......\CVS
...........................\.....\.......\...\Entries
...........................\.....\.......\...\Repository
...........................\.....\.......\...\Root
...........................\.....\.......\i2c_slave_model.v
...........................\.....\.......\spi_slave_model.v
...........................\.....\.......\tst_bench_top.v
...........................\.....\.......\wb_master_model.v
...........................\doc
...........................\...\CVS
...........................\...\...\Entries
...........................\...\...\Repository
...........................\...\...\Root
...........................\...\i2c_specs.pdf
...........................\...\src
...........................\...\...\CVS
...........................\...\...\...\Entries
...........................\...\...\...\Repository
...........................\...\...\...\Root
...........................\...\...\I2C_specs.doc
...........................\rtl
...........................\...\CVS
...........................\...\...\Entries
...........................\...\...\Repository
...........................\...\...\Root
...........................\...\verilog
...........................\...\.......\CVS
...........................\...\.......\...\Entries
...........................\...\.......\...\Repository
...........................\...\.......\...\Root
...........................\...\.......\i2c_master_bit_ctrl.v
...........................\...\.......\i2c_master_byte_ctrl.v
...........................\...\.......\i2c_master_defines.v
...........................\...\.......\i2c_master_top.v
...........................\...\.......\timescale.v
...........................\...\vhdl
...........................\...\....\CVS
...........................\...\....\...\Entries
...........................\...\....\...\Repository
...........................\...\....\...\Root
...........................\...\....\I2C.VHD
...........................\...\....\i2c_master_bit_ctrl.vhd
...........................\...\....\i2c_master_byte_ctrl.vhd
...........................\...\....\i2c_master_top.vhd
...........................\...\....\readme
...........................\...\....\tst_ds1621.vhd
...........................\sim
...........................\...\CVS
...........................\...\...\Entries
...........................\...\...\Repository
...........................\...\...\Root
...........................\...\i2c_verilog
...........................\...\...........\CVS
...........................\...\...........\...\Entries
...........................\...\...........\...\Repository
...........................\...\...........\...\Root
...........................\...\...........\run
...........................\...\...........\...\bench.vcd
...........................\...\...........\...\CVS
...........................\...\...........\...\...\Entries
...........................\...\...........\...\...\Repository
...........................\...\...........\...\...\Root
...........................\...\...........\...\INCA_libs
...........................\...\...........\...\.........\CVS
...........................\...\...........\...\.........\...\Entries
...........................\...\...........\...\.........\...\Repository
...........................\...\...........\...\.........\...\Root
...........................\...\...........\...\ncverilog.key
...........................\...\...........\...\ncverilog.log
...........................\...\...........\...\run
...........................\...\...........\...\waves
...........................\...\...........\...\.....\CVS
...........................\...\...........\...\.....\...\Entries
...........................\...\...........\...\.....\...\Repository
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